Comparator unit for a flash analog-to-digital converter

• US 4,910,518 A
• Filed: 07/14/1988
• Issued: 03/20/1990
• Est. Priority Date: 07/16/1987
• Status: Expired due to Term

• Current Assignee: Samsung Semiconductor and Telecommunications Company (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Semiconductor and Telecommunications Company (Samsung Electronics Co. Ltd.)
• Inventors: Myung, Chan-Kyu, Kim, Heung-Suck
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Kim, Helen
• Application Number:
  US07/218,843
• Time in Patent Office: 614 Days
• Field of Search: 341/120, 341/139, 341/140, 341/155, 341/160, 330/310, 330/254, 330/258
• US Class Current: 341/155
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/287 using additional transistors in the feedback circuit H03K3/289 takes precedence
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration
• CPC Class Codes: H03K 5/2418 with at least one differential stage
• CPC Class Codes: H03K 5/2427 using clock signals

Abstract

A high speed comparator unit for a flash A/D converter in which a bank of comparator units compare simultaneously an analog input voltage with equally spaced reference voltages, and an encoder ROM produces digital signals based on the comparator unit'"'"'s outputs. The comparator unit includes a two-stage cascode configuration and a level shifter configuration which effectively reduces the miller-effect of the comparator unit.

Claims

1. A comparator unit for a flash A/D converter having a plurality of comparator units and an encoder ROM, each said comparator unit comprising:

switching transistors which switch conductive states based upon a clock input signal;

comparing transistors having a single output for comparing an input voltage to a reference voltage, said comparing transistors having their output connected to one of said switching transistors;

latching transistors for latching the output voltage of the comparing transistors, said latching transistors being connected to said comparing transistors and said switching transistors and latch based upon the input clock signal;

miller-capacitance reducing means for reducing a miller capacitance effect of said latching transistors, said miller effect reducing means comprising a pair of transistors having a constant d.c. power input and whose output is connected to said latching transistors and said comparing transistors;

first and second signal transistors being connected to said miller-capacitance reducing means and said latching transistors for generating a signal to an output means; and

said output means outputting said compared output voltage to an encoder ROM based upon the comparison of the input voltage and the reference voltage.

2. The comparator unit according to claim 1 wherein said miller-capacitance reducing means comprises level shifting means coupled between said latching transstors and said first and second signal transistors.

3. The comparator unit of claim 2 wherein said level shifting means comprises a pair of transistors in cascade arrangement connected between the first signal transistor and a latch transistor and a pair of transistors in cascade arrangement connected between the second signal transistor and a latch transistor.

4. A comparator unit for a flash A/D converter comprising:

a first switch transistor having a base connected to a clock signal, a collector, and an emitter;

a second switch transistor having a base connected to an inverted clock signal, a collector, and an emitter;

a pair of comparing transistors having their bases connected to voltage signals to be compared, collectors, and emitters connected to the collector of said first switch transistor;

a first latch transistor having a base, a collector connected to the collector of one of said comparing transistors, and an emitter connected to the collector of said second switch transistor;

a second latch transistor having a base, a collector connected to the collector of another of said comparing transistors, and an emitter connected to the collector of said second switch transistor;

a first resistor and a second resistor each having a first terminal and a second terminal;

a first signal transistor having a base connected to a first voltage source, a collector connected to an enable line of a first adjacent comparator unit, and an emitter connected to a second terminal of said first resistor;

a second signal transistor having a base connected to the first voltage source, a collector connected to an enable line of a second adjacent comparator unit, and an emitter connected to a second terminal of said second resistor;

a third resistor having a first terminal connected to the collector of said second signal transistor and a second termial connected to a voltage supply;

a third signal transistor having a base connected to the collector of said second signal transistor, a collector connected to the voltage supply, and an emitter connected to an output; and

a miller-capacitance reducer, having a plurality of transistors, each of the transistors being connected to at least one of the collectors of said comparing transistors, the base of said first and second latch transistors, and the first terminal of said first and second resistors.

5. A comparator unit according to claim 4 wherein said miller-capacitance reducer comprises:

a pair of cascode transistors having their bases connected to a second power source, their collectors connected to the second terminals of said first and second resistors, and their emitters connected to the collectors of one of said pair of comparing transistors and to one of said first and second latch transistors; and

level shifting transistors coupled between the collector of one of said pair of cascode transistors and the bases of said first latch transistor and said second latch transistor.

6. A comparator unit according to claim 5 wherein said second level transistors function as one of a resistor and a diode.

7. A comparator unit according to claim 4 wherein said level shifting transistors comprise two pairs of transistors, a first pair coupled between one of said cascode transistors and the base of said first latch transistor, and a second pair coupled between another of said cascode transistors and the base of said second latch transistor, each pair comprising:

a first level transistor connected to the respective collector of said cascode transistors; and

a second level transistor connected to said first level transistor and the respective bases of said first latch transistor and said second latch transistor.