Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell

• US 4,910,709 A
• Filed: 08/10/1988
• Issued: 03/20/1990
• Est. Priority Date: 08/10/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, Sang H., Lu, Nicky C., Henkels, Walter H.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US07/230,410
• Time in Patent Office: 587 Days
• Field of Search: 365/149
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

Claims

1. A memory cell structure for a dynamic semiconductor memory array of the type including pairs of wordlines having a first wordline for transmitting a first wordline signal manifesting first and second signal levels and a second wordline for transmitting a second wordline signal manifesting two signal levels complementary to said first and second signal levels of said first wordline signal, said memory array further including bit lines,

said memory cell structure being connected between a bit line and a pair of wordlines of said memory array and comprising an NMOS type transistor device including first, second and gate electrodes,

a PMOS type transistor device including first, second and gate electrodes, and

a storage capacitor wherein said first electrode of said NMOS type transistor device is connected to said first electrode of said PMOS type transistor device and to a bit line of said memory array, and said second electrode of said NMOS type transistor device is connected to said second electrode of said PMOS type transistor device and to said storage capacitor,

said gate electrode of said NMOS type transistor device is connected to said first wordline of said pair and said gate electrode of said PMOS type transistor device is connected to said second wordline of said pair, said NMOS and PMOS type transistor devices both being turned off in response to a first signal level on said first wordline and said complementary signal level thereof on said second wordline, and said NMOS and PMOS type transistor devices being both turned on in response to a second signal level on said first wordline and said complementary signal level thereof on said second wordline, and

wherein said bit line is electrically connected to said storage capacitor and charge is stored into and read out from said storage capacitor in response to said NMOS and PMOS type transistor devices being turned on and off by said signals on said wordlines.

2. A memory cell according to claim 1 wherein said first electrodes of said NMOS type transistor device is a source electrode and said first electrode of said PMOS type transistor device is a drain electrode, and said second electrode of said NMOS type transistor device is a drain electrode and said second electrode of said PMOS type transistor device is a source electrode.

3. A memory cell according to claim 1 wherein said first electrode of said NMOS type transistor device is a drain electrode, and said second electrodes of said NMOS type transistor device is a source electrode, said first electrode o said PMOS type transistor device is a source electrode, and said second electrode of said PMOS type transistor device is a drain electrode.

4. A memory cell according to claim 1 including a semiconductor substrate,

an epitaxial silicon layer disposed on said substrate,

an n-well region implanted in said epitaxial layer,

a polysilicon filled trench disposed in said substrate and epitaxial layers and insulated therefrom to form said storage capacitor,

said PMOS type transistor device disposed on said epitaxial layer and including source and drain impurity regions implanted into said n-well region and an oxide covered gate electrode disposed over said n-well region proximate to said source and drain regions,

said NMOS type transistor device vertically disposed over said PMOS type transistor device and including source and drain impurity regions disposed over and electrically connected to said source and drain regions of said PMOS type transistor device, and, an oxide covered gate electrode disposed over and electrically isolated from said gate electrode of said PMOS type transistor device.

5. A memory cell according to claim 4 further including a layer of conductive material disposed over said polysilicon filled trench, over said source region of said PMOS type transistor device and beneath said source region of said NMOS type transistor device to electrically connected said trench storage capacitor to said source regions.

6. A memory cell according to claim 4 wherein said substrate is composed of p+type silicon, said epitaxial silicon layer is p type, said polysilicon filled in said trench is p+type, said n-well is composed of a phosphorous implant and said source and drain regions of said PMOS and NMOS type transistor devices are formed of phosphorus and boron implants to provide graded source/drain junctions.