Semiconductor integrated circuit with self-testing
First Claim
1. A semiconductor integrated circuit comprising:
- integrated circuit blocks connected in series for testing a system formed on said semiconductor integrated circuit, the system having a first stage and a following stage each including at least one of said integrated circuit blocks, each of said integrated circuit blocks comprising;
logic means for carrying out a logic operation and providing output data signals corresponding thereto;
an input terminal receiving input signals supplied to the integrated circuit blocks;
pseudo-random pattern generating means for generating a pseudo-random pattern signal;
data compressing means for receiving and compressing the output data signals supplied from said logic means to generate a compressed data signal; and
an output terminal, operatively connected to said logic means, for receiving the output data signal from said logic means and for directly supplying the same to said input terminal of the integrated circuit blocks corresponding to the following stage,wherein at least one of said integrated circuit blocks of the first stage include first switching means for connecting said pseudo-random pattern generating means thereof to said logic means thereof during testing of the system, andwherein each of said integrated circuit blocks of the following stage include second switching means for connecting said input terminal thereof to said logic means thereof during testing of the system.
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Accused Products
Abstract
A semiconductor integrated circuit comprises a plurality of integrated circuit blocks constructed on a wafer. The integrated circuit blocks are electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logic circuit for carrying out a logic operation, a pseudo-random pattern generating circuit for generating a pseudo-random pattern signal, a switching circuit for selecting either an input signal to be processed by the logic circuit or the pseudo-random pattern signal and a data compressing circuit for compressing an output data signal of the logic circuit. The switching circuit is responsive to a test enabling signal which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode, and outputs the selected signal to the logic circuit.
86 Citations
12 Claims
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1. A semiconductor integrated circuit comprising:
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integrated circuit blocks connected in series for testing a system formed on said semiconductor integrated circuit, the system having a first stage and a following stage each including at least one of said integrated circuit blocks, each of said integrated circuit blocks comprising; logic means for carrying out a logic operation and providing output data signals corresponding thereto; an input terminal receiving input signals supplied to the integrated circuit blocks; pseudo-random pattern generating means for generating a pseudo-random pattern signal; data compressing means for receiving and compressing the output data signals supplied from said logic means to generate a compressed data signal; and an output terminal, operatively connected to said logic means, for receiving the output data signal from said logic means and for directly supplying the same to said input terminal of the integrated circuit blocks corresponding to the following stage, wherein at least one of said integrated circuit blocks of the first stage include first switching means for connecting said pseudo-random pattern generating means thereof to said logic means thereof during testing of the system, and wherein each of said integrated circuit blocks of the following stage include second switching means for connecting said input terminal thereof to said logic means thereof during testing of the system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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- 11. A wafer-scale integrated circuit for testing a complete system, said wafer-scale integrated circuit comprising logic blocks forming the complete system to be tested, each logic block including self-test means for testing said logic block corresponding thereto, said self-test means of at least one of said logic blocks is further for testing the complete system.
Specification