Ion implanted JFET with self-aligned source and drain

• US 4,912,053 A
• Filed: 02/01/1988
• Issued: 03/27/1990
• Est. Priority Date: 02/01/1988
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Schrantz, Gregory A.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/151,184
• Time in Patent Office: 785 Days
• Field of Search: 437/29, 437/56, 437/152, 437/154, 437/30, 437/41, 437/200, 437/160, 437/162, 357/22
• US Class Current: 438/188
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A method of fabricating I² JFETs including separately and in combination out-diffusion of impurities from doped source and drain contact material to product self-aligned source and drains; using the source and drain contacts as mask to form a self-aligned top gate spaced from the source and drain; and dual ion implantation of the channel for increasing radiation hardness.

Claims

1. A method for fabricating junction field effect transistors comprising:

introducing first and second conductivity type impurities into a first surface of a substrate of said first conductivity type by ion implantation to form a top gate of said first conductivity type and a channel of said second conductivity type between a said substrate, which is a bottom gate, and said top gate;

depositing contact material including second conductivity type impurities at two spaced positions along said surface of said substrate; and

heating to simultaneously activate said ion implanted impurities to form said top gate and channel and diffuse said second conductivity type impurities from said contact material into said channel to form source and drain with self-aligned contacts.

2. A method according to claim 1, wherein said depositing step is performed after said introducing step.

3. A method according to claim 2, wherein said depositing step is performed at a low temperature.

4. A method according to claim 1, wherein said introducing step includes first introducing said second conductivity type impurities to form said channel before said depositing step and second introducing said first conductivity type impurities to form said top gate after said depositing step.

5. A method according to claim 4, wherein said second introducing step is performed to form a top gate spaced from said contact material at said surface of said substrate.

6. A method according to claim 5, including selecting said impurities so that said top gate is spaced from said source and drain and said channel is deeper than said source and drain after said heating step.

7. A method according to claim 4, wherein said substrate includes a thick layer of field insulator on a surface;

and including;

the preliminary steps of forming an opening in said field insulator to expose a portion of said substrate in which said subsequent introducing and depositing steps are to be performed;

forming a thin insulator layer in said opening; and

forming contact apertures in said thin insulator layer before said depositing step.

8. A method according to claim 7, including patterning said contact material to form a contact portion extending across said thin insulator layer to be used as a mask during said second introducing step to form a top gate spaced from said contact material at said surface of said substrate

9. A method according to claim 1, wherein said depositing includes depositing a doped polycrystalline silicon and a refractory metal to form a polycrystalline silicide.

10. A method according to claim 1, wherein said substrate includes a thick layer of field insulator on a surface;

and including;

the preliminary steps of forming an opening in said field insulator to expose a portion of said substrate in which said subsequent introducing and depositing step are to be performed; and

forming a thin insulator layer in said opening; and

forming contact apertures in said thin insulator layer before said depositing step.

11. A method according to claim 1, wherein said depositing step includes patterning said contact material to form contact portions and is performed before said introducing step;

and

said contact portions are used as a mask during said introducing step.

12. A method for fabricating junction field effect transistors comprising:

introducing a second conductivity type impurities into a first surface of a substrate of a first conductivity type to form a channel of said second conductivity type;

introducing second conductivity type impurities into said substrate through contact apertures in an insulating layer on said first surface to form spaced source and drains of said second conductivity type in said channel;

depositing and patterning contact material to form a contact to said substrate through said contact apertures for said source and drain and a portion extending across said insulating layer; and

introducing first conductivity type impurities into said channel using said contact material as a mask to form a top gate of said first conductivity type in said channel and spaced from said source and drain.

13. A method according to claim 12, wherein all said introducing steps are performed by ion implantation and including heating the substrate subsequent to all said ion implantations to activate said ion implanted impurities to form said top gate, channel, source and drain.

14. A method according to claim 12, wherein introducing said impurities to form said source and drain includes depositing contact material including said second conductivity type impurities;

wherein introducing said impurities to form said channel and top gate includes ion implantation; and

including heating said substrate subsequent to all introducing steps to diffuse said second conductivity type impurity from said contact material into said channel to form said source and drain and activating said ion implanted impurities to form said top gate and channel.

15. A method of fabricating complementary junction field effect transistors comprising:

(a) selectively introducing impurities of a first conductivity type into a first bottom gate of a second conductivity type to form a first channel of a first conductivity type;

(b) selectively introducing impurities of a second conductivity type into a second bottom gate of a first conductivity type to form a second channel of a second conductivity type;

(c) selectively introducing impurities of a first conductivity type into said first channel to form spaced first source and first drain of said first conductivity type in said first channel;

(d) selectively introducing impurities of a second conductivity type into second channel to form spaced second source and second drain of said second conductivity type in said second channel,

(e) selectively introducing impurities of a second conductivity type into said first channel to form a top gate of said second conductivity type in said first channel and spaced from said first source and first drain;

(f) selectively introducing impurities of a first conductivity type into said second channel to form a top gate of said first conductivity type in said second channel and spaced from said second source and second drain;

(g) forming first source and drain contact apertures in a thin insulator layer over said first channel prior to step c;

(h) forming second source and drain contact apertures in a thin insulator layer over said second channel prior to step d; and

(i) depositing and patterning a contact material to form source and drain contacts having a portion extending across said thin insulator prior to steps e and f to be used as a mask during steps e and f to form said first and second top gate spaced from a respective source and drain.

16. A method according to claim 15, wherein steps a through f are performed by ion implantation and further including heating to simultaneously activate all ion implanted impurities to form said first and second channels, sources, drains and top gates.

17. A method according to claim 15, wherein:

steps g and h are performed simultaneously prior to steps c and d;

step c includes selectively introducing said first conductivity type impurities into first portions of said contact material in said first source and drain contact apertures;

step d includes selectively introducing said second conductivity type impurities into second portions of said contact material in said second source and drain apertures;

steps a, b, e and f are performed by ion implantation; and

including heating to simultaneously active all ion implanted impurities and diffuse impurities from said contact material into said channels to form said first and second channels, top gates, sources and drains.

18. A method according to claim 15, wherein step e includes forming a mask covering said second channel and exposing said first channel and said first source and drain contacts, and step f includes forming a mask covering said first channel and exposing said second channel and said second source and drain contacts.

19. A method for fabricating junction field effect transistors comprising:

introducing second conductivity type impurities into a first surface of a substrate of a first conductivity type to a first depth and first impurity concentration to form an active channel;

introducing second conductivity type impurities into said substrate to a second depth and second impurity concentration less than said first depth and first impurity concentration to form an enhanced channel region at said surface of said active channel;

introducing second conductivity type impurities into said substrate to form spaced source and drains of said second conductivity type in said active channel and enhanced channel region; and

introducing first conductivity type impurities into said channel to form a top gate of said first conductivity type in said channel and spaced from said source and drain.

20. A method according to claim 19, wherein said introducing steps for forming said channel are performed by ion implantation through a thin insulative layer on said substrate and said introducing step to form said enhanced channel region is performed to have a peak concentration at an interface of said substrate and said insulative layer.

21. A method of fabricating complementary junction field effect transistors comprising:

(a) selectively introducing impurities of a first conductivity type into a first bottom gate of a second conductivity type to a first depth and first impurity concentration to form a first active channel of a first conductivity type;

(b) selectively introducing first conductivity type impurities into said first active channel to a second depth and second impurity concentrations less than said first depth and first impurity concentration to form a first enhanced channel region at the surface of said first active channel;

(c) selectively introducing impurities of second conductivity type into a second bottom gate of a first conductivity type to a third depth and third impurity concentration to form a second active channel of a second conductivity type;

(d) selectively introducing second conductivity type impurities into said second active channel to a fourth depth and fourth impurity concentration less than said third depth and third impurity concentration to form a second enhanced channel region at the surface of said second active channel;

(e) selectively introducing impurities of a first conductivity type into said first active channel and first enhanced channel region to form spaced first source and first drain of said first conductivity type in said first active channel;

(f) selectively introducing impurities of a second conductivity type into said second active channel and second enhanced channel region to form spaced second source and second drain of said second conductivity type in said second active channel;

(g) selectively introducing impurities of a second conductivity type into said first active channel and first enhanced channel region to form a top gate of said second conductivity type in said first active channel and spaced from said first source and first drain at the surface by said first enhanced channel region; and

(h) selectively introducing impurities of a first conductivity type into said second active channel and second enhanced channel region to form a top gate of said first conductivity type in said second active channel and spaced from said second source and second drain at the surface by said second enhanced channel region.

22. A method according to claim 21, wherein steps a, b, c and d are performed by ion implantation through a thin insulator layer on said first and second bottom gates and steps b and d are performed to have a peak concentration at an interface of said first bottom gate and said thin insulator layer and at an interface of said second bottom gate and said thin insulator layer, respectively.