Programmable logic device with array blocks with programmable clocking

• US 4,912,342 A
• Filed: 09/14/1989
• Issued: 03/27/1990
• Est. Priority Date: 05/05/1988
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: So, Hock-Chuen, Wong, Sau-Ching, Hartmann, Robert F., Kopec, Stanley J. Jr.
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/407,411
• Time in Patent Office: 194 Days
• Field of Search: 307/465, 307/468, 307/469, 307/480, 307/481, 307/269, 364/716
• US Class Current: 326/40
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset

Abstract

A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.

Claims

1. In a programmable logic device having (1) a plurality of word line conductors;

(2) a plurality of P-term line conductors, each of which is programmably interconnectable to at least some of said word line conductors for producing on each P-term line conductor a signal which is a logical function of the signals on the word line conductors to which that P-term line conductor is interconnected; and

(3) a clock signal utilization device for processing a signal derived from at least one first P-term line conductor in accordance with an applied clock signal, the improvement comprising;

means for providing a first signal which can be selected to be either a synchronous clock signal or a constant signal;

means associated with at least one second P-term line conductor for allowing the signal on said second P-term line conductor to be made a constant signal; and

means for logically combining said first signal and a signal derived from the signal on said second P-term line conductor to produce said applied clock signal.

2. The apparatus defined in claim 1 wherein said means for logically combining said first signal and said signal derived from the signal on said second P-term line conductor comprises an OR gate.