VCO controlled by separate phase locked loop

• US 4,912,433 A
• Filed: 05/16/1989
• Issued: 03/27/1990
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suzuki, Satoshi, Muroga, Hiroki, Motegi, Hiroyuki
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/352,540
• Time in Patent Office: 315 Days
• Field of Search: 331/1 R, 331/2, 331/8, 331/17, 331/25, 331/27, 331/57, 331/34, 358/191.1, 358/194.1, 358/195.1, 455/260
• US Class Current: 331/8
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence

Abstract

A voltage controlled oscillator (VCO) is controlled by a separate phase locked loop (PLL). The PLL includes a first variable delay circuit of m stages which receives a reference frequency signal and produces a delayed signal which is compared in a phase comparator with the reference frequency signal. A first control signal generating circuit in the PLL receives the output of the phase comparator and a reference voltage to produce a first control signal for controlling the delay of the first variable delay circuit. The VCO contains a ring oscillator formed of a second variable delay circuit of n stages similar to those of the first variable delay circuit. A second control signal generating circuit in the VCO receives the output of the phase comparator and a control voltage to produce a second control signal for controlling the delay of the second variable delay circuit to thereby control the output frequency of the VCO.

Claims

1. A voltage controlled oscillator circuit comprising:

a PLL section for supplying a deviation signal according to a received reference frequency signal and a received reference voltage; and

a VCO section for supplying an oscillation output according to the deviation signal and a received control voltage;

said PLL section comprising;

first delay means for delaying the reference frequency signal according to first delay control signal and outputting a delay signal;

phase difference detection means for comparing the phase of the reference frequency signal with that of the delay signal and outputting the deviation signal based on the phase difference; and

first delay control means for outputting the first delay control signal having a signal level corresponding to the reference voltage and the deviation signal.

2. A circuit according to claim 1, wherein the delay time caused by said first delay means is selected to be substantially one-half the period of the reference frequency signal.

3. A circuit according to claim 1, wherein said VCO section includes:

second delay control means for outputting a second delay control signal producing a signal level corresponding to the control voltage and the deviation signal; and

second delay means for cyclically delaying the oscillation output according to the second delay control signal and generating the oscillation output.

4. A circuit according to claim 1, wherein said first delay means includes:

a plurality of transmission gates; and

a plurality of inverters alternately series-connected to said plurality of transmission gates; and

the first delay control signal is used as gate inputs of said plurality of transmission gates.

5. A circuit according to claim 3, wherein said second delay means includes:

a plurality of transmission gates; and

a plurality of inverters alternately series-connected to said plurality of transmission gates; and

the second delay control signal is used as gate inputs of said plurality of transmission gates.

6. A circuit according to claim 1, wherein said first delay means includes:

a plurality of CMOS transmission gates; and

a plurality of inverters alternately series-connected to said plurality of CMOS transmission gates; and

the first delay control signal is used as gate inputs of one channel type gates of said plurality of CMOS transmission gates and an inverted signal of the first delay control signal is used as gate inputs of the other channel type gates of said plurality of CMOS transmission gates.

7. A circuit according to claim 3, wherein said second delay means includes:

a plurality of CMOS transmission gates; and

a plurality of inverters alternately series-connected to said plurality of CMOS transmission gates; and

the second delay control signal is used as gate inputs of one channel type gates of said plurality of CMOS transmission gates and an inverted signal of the second delay control signal is used as gate inputs of the other channel type gates of said plurality of CMOS transmission gates.

8. A circuit according claim 1, wherein said phase difference detecting means includes:

a first D-type flip-flop clocked by the reference frequency signal;

a second D-type flip-flop clocked by the delay signal;

means for resetting said first and second D-type flip-flops according to the logical product of Q outputs of said first and second D-type flip-flops;

a first transistor of a first conductivity type driven by an inverted signal of the Q output of said first D-type flip-flop;

a second transistor of a second conductivity type driven by the Q output signal of said second D-type flip-flop; and

means for deriving the deviation signal from a signal which is obtained by combining outputs of said first and second transistors.

9. A circuit according to claim 8, wherein said deriving means includes a low-pass filter for filtering the combined signal to output the deviation signal.

10. A circuit according to claim 1, wherein said first delay control means includes:

a first MOS transistor of a first conductivity type having a gate supplied with the deviation signal, a source connected to a first power source circuit and a drain for outputting the first delay control signal;

a second MOS transistor of the first conductivity type having a source connected to said first power source circuit and a drain and a gate connected to the drain of said first MOS transistor; and

a third MOS transistor of a second conductivity type having a gate supplied with the reference voltage, a source connected to a second power source circuit and a drain connected to the drain of said first MOS transistor.

11. A circuit according to claim 3, wherein said second delay control means includes:

a first MOS transistor of a first conductivity type having a gate supplied with the deviation signal, a source connected to a first power source circuit and a drain for outputting the first delay control signal;

a second MOS transistor of the first conductivity type having a source connected to said first power source circuit and a drain and a gate connected to the drain of said first MOS transistor; and

a third MOS transistor of a second conductivity type having a gate supplied with the control voltage, a source connected to a second power source circuit and a drain connected to the drain of said first MOS transistor.

12. A circuit according to claim 10, wherein said first delay control means further includes:

a fourth MOS transistor of the second conductivity type having a gate supplied with a preset bias voltage, a source connected to said second power source circuit and a drain connected to the drain of said first MOS transistor.

13. A circuit according to claim 11, wherein said second delay control means further includes:

a fourth MOS transistor of the second conductivity type having a gate supplied with a preset bias voltage, a source connected to said second power source circuit and a drain connected to the drain of said first MOS transistor.

14. A circuit according to claim 10, wherein said first delay control means further includes:

a fourth MOS transistor of tee second conductivity type having a source connected to said second power source circuit, and a gate and a drain connected to the drain of said first MOS transistor.

15. A circuit according to claim 11, wherein said second delay control means further includes:

a fourth MOS transistor of the second conductivity type having a source connected to said second power source circuit, and a gate and a drain connected to the drain of said first MOS transistor.

16. A circuit according to claim 1, wherein said first delay control means includes:

a first MOS transistor of a first conductivity type having a gate supplied with the deviation signal, a source connected to a first power source circuit and a drain for outputting the first delay control signal;

a second MOS transistor of the first conductivity type having a source connected to said first power source circuit, a gate supplied with a preset bias voltage and a drain connected to the drain of said first MOS transistor; and

a third MOS transistor of a second conductivity type having a gate supplied with the reference voltage, a source connected to a second power source circuit and a drain connected to the drain of said first MOS transistor.

17. A circuit according to claim 3, wherein said second delay control means includes:

a first MOS transistor of a first conductivity type having a gate supplied with the deviation signal, a source connected to a first power source circuit and a drain for outputting the first delay control signal;

a second MOS transistor of the first conductivity type having a source connected to said first power source circuit, a gate supplied with a preset bias voltage and a drain connected to the drain of said first MOS transistor; and

a third MOS transistor of a second conductivity type having a gate supplied with the control voltage, a source connected to a second power source circuit and a drain connected to the drain of said first MOS transistor.

18. A frequency synthesizer type tuning system comprising:

a PLL section for outputting a deviation signal according to a preset reference frequency signal and a preset reference voltage;

a VCO section for outputting an oscillation output having a frequency corresponding to a preset control voltage and the deviation signal;

a tuner section for generating an intermediate frequency signal of a preset frequency which is obtained by frequency-converting a high frequency input signal, using a beat between the high frequency input signal and the oscillation output; and

a microcomputer section for supplying data corresponding to the reference voltage and the control voltage to said PLL section and VCO section;

wherein said PLL section comprises;

first delay means for delaying the reference frequency signal according to a first delay control signal and outputting a delay signal;

phase difference detection means for comparing the phase of the reference frequency signal with that of the delay signal and outputting the deviation signal based on the detected phase difference; and

first delay control means for generating the first delay control signal having a signal level corresponding to a preset reference voltage and the deviation signal.

19. A tuning system according to claim 18, wherein said VCO section includes:

second delay control means for generating a second delay control signal having a signal level corresponding to the control voltage and the deviation signal; and

second delay means for cyclically delaying the oscillation output according to the second control signal and generating the oscillation output.

20. A voltage controlled oscillator circuit comprising:

a phase-locked loop section which includes first delay means, having cascade-connected m-stage delay sections whose delay times are controlled by a control signal, for delaying a reference frequency signal by a predetermined period;

phase difference voltage generating means for generating a phase difference voltage corresponding to a phase difference between the output of said first delay means and the reference frequency signal; and

first control signal generating means for generating the control signal for determining the signal delay times o the respective delay sections of said first delay means based on a reference voltage and the phase difference voltage; and

a voltage controlled oscillator section which includes second delay means, including cascade-connected n-stage delay sections having structures equivalent to those of the delay sections of said first delay means, wherein an output of said second delay means is fed back to the input terminal thereof so that a ring oscillator circuit is constituted; and

second control signal generating means for generating a control signal for determining the signal delay times of the respective delay sections of said second delay means based on the phase difference voltage and a control voltage for controlling the output frequency.

21. A circuit according to claim 20, wherein each of the delay sections of said first and second delay means includes a first transmission gate;

an inverter supplied with the output of said first transmission gate;

a second transmission gate supplied with the output of said inverter; and

an inverter supplied with the output of said second transmission gate.

22. A circuit according to claim 21, wherein each of said first and second control signal generating means includes a first transistor of a first conductivity type whose source-drain path is connected between a first voltage terminal and a first output node and whose gate is supplied with the phase difference voltage;

a second transistor of the first conductivity type whose source-drain path is connected between said first voltage terminal and said first output node and whose gate is connected to said first output node; and

a third transistor of a second conductivity type whose source-drain path is connected between a second voltage terminal and said first output node and whose gate is supplied with either the reference voltage or the control voltage;

signals of the first output nodes of said first and second control signal generating means being supplied to said first and second transmission gates of each of the delay sections o said first and second delay means.

23. A circuit according to claim 20, 21, or 22, wherein each of the delay sections of said first and second delay means includes a first CMOS transmission gate formed of P-channel and N-channel transistors;

an inverter supplied with the output of said first CMOS transmission gate;

a second CMOS transmission gate formed of P-channel and N-channel transistors supplied with the output of said inverter; and

an inverter supplied with the output of said second CMOS transmission gate.

24. A circuit according to claim 23, wherein each of said first and second control signal generating means includes:

a first transistor of a first conductivity type whose source-drain path is connected between a first voltage terminal and a first output node and whose gate is supplied with the phase difference voltage;

a second transistor of the first conductivity type whose source-drain path is connected between said first voltage terminal and said first output node and whose gate is connected to said first output node;

a third transistor of a second conductivity type whose source-drain path is connected between a second voltage terminal and said first output node and whose gate is supplied with either the reference voltage or the control voltage;

a fourth transistor of the first conductivity type whose source-drain path is connected between said first voltage terminal and a second output node and whose gate is connected to said first output node; and

a fifth transistor of the second conductivity type whose source-drain path is connected between said second voltage terminal and said second output node and whose gate is connected to said second output node.

25. A circuit according to claim 24, wherein signals of the first output nodes of said first and second control signal generating means are supplied to the P-channel transistors of said first and second CMOS transmission gates of each of the delay sections of said first and second delay means and signals of the second output nodes of said first and second control signal generating means are supplied to the N-channel transistors of said first and second CMOS transmission gates of each of the delay sections of said first and second delay means.