Multiple processor communications system

• US 4,912,623 A
• Filed: 04/11/1988
• Issued: 03/27/1990
• Est. Priority Date: 04/11/1988
• Status: Expired due to Term

• Current Assignee: Schneider Automation Incorporated (Schneider Electric SE)
• Original Assignee: Square D Company (Schneider Electric SE)
• Inventors: Rantala, Glen W., Janke, Donald R.
• Primary Examiner(s): MacDonald, Allen
• Application Number:
  US07/179,969
• Time in Patent Office: 715 Days
• Field of Search: 364/131-138, 364/140
• US Class Current: 700/7
• CPC Class Codes: G05B 19/052 Linking several PLC's

Abstract

A multiple processor communications system including a control processor and a scan processor having its own program counter enabling the efficient execution of subroutines. The scan processor directly accesses a compiled user memory which contains its operating program and also directly accesses the image memory which contains the input and output data to perform the computations required by the program. The system includes error codes for distinguishing various error conditions including collision error conditions indicating illegal commands to the scan processor when it is scanning and parity errors in the compiled user memory and in the image memory.

Claims

1. A programmable logic controller comprising:

a user memory for containing executable instructions,

an image memory for receiving and storing the state of inputs, outputs and register values;

a scan processor coupled to said user memory and said image memory for performing said instructions stored in said user memory to compute the output states and register values of said image memory, said scan processor including a program counter indicating an address of said next instruction to be performed, a stack and means responsive to one of said instructions for moving said address of said next instruction to be performed from said program counter to said stack and for inserting an address of a different one of said instructions to be performed in said program counter, thereby causing said scan processor to perform said different instruction, and means for moving said moved address from said stack to said program counter upon completion of said different one of said instructions and;

a control processor coupled to said user memory, said control processor providing management communication and supervisory functions for the system, said control processor including means for moving said address of said next instruction to be performed from said program counter to said stack and for inserting an address of a different one of said instructions to be performed in said program counter, thereby causing said scan processor to perform said different instruction, and means for moving said moved address from said stack to said program counter upon completion of said different one of said instructions.

2. A programmable logic controller as defined in claim 1, wherein the scan processor directly accesses said compiled user memory for executive instructions.

3. The programmable logic controller of claim 1 wherein said executable instructions comprise a ladder program.

4. The programmable logic controller of claim 1 wherein:

said different one of said instructions comprises a first instruction of a subroutine; and

said moved address is moved from said stack to said program counter upon completion of said subroutine.

5. A programmable logic controller comprising:

a user memory for containing executable instructions including a ladder program comprising a routine and a subroutine, said routine including an subroutine instruction to execute said subroutine;

an image memory for receiving and storing the state of inputs, outputs and register values;

a scan processor coupled to said user memory and said image memory for performing sequential steps of said routines and subroutines to compute the output states and register values of said image memory, said scan processor including a program counter indicating an address of said instruction of said next step to be performed, a stack and means responsive to said subroutine instruction for moving said address of said instruction contained in said program counter to said stack and for inserting an address of said first instruction of said subroutine in said program counter to cause said scan processor to perform said subroutine, and means for moving said moved address from said stack to said program counter upon completion of said subroutine and;

a control processor coupled to said user memory, said control processor providing management communication and supervisory functions for the system, said control processor including means for moving said address stored in said program counter to said stack and for inserting an address of a different one of said instructions to be performed in said program counter to cause said scan processor to perform said different instruction, and means for moving said moved address from said stack to said program counter upon completion of said different one of said instructions.