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Hit predictive cache memory

  • US 4,912,626 A
  • Filed: 03/15/1988
  • Issued: 03/27/1990
  • Est. Priority Date: 03/25/1987
  • Status: Expired due to Fees
First Claim
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1. A hit predictive cache memory including an associative memory containing addresses of operands stored in a working memory and a fast memory containing the operands corresponding to said addresses, said associative memory when interrogated by a central processing unit providing a hit or miss signal respectively to indicate when a requested operand is actively present or not present in said fast memory, said predictive cache memory further comprising:

  • control logic means comprising at least a storage element for storing a hit or miss condition occurring during a preceding interrogation of said cache memory and for providing as an output, a corresponding prehit premiss indicator signal;

    first logic circuit means coupled to receive memory read interrogation signals from said central processing unit, and said indicator signal from said control logic means, said first logic circuit means providing a signal indicative of operand present in said cache memory to said central processing unit irrespective of the actual presence of said operand when said indicator signal is a prehit indicator, said actual presence of said operand in said cache being subsequently confirmed or non-confirmed by said associative memory; and

    second logic circuit means coupled to receive said miss signal from said associative memory and said signal indicative of operand present in said cache memory from said first logic circuit means, said second logic circuit means generating an error signal for delivery to said central processing unit and a reset signal to said storage element of said control logic means in response to the joint receipt of said miss signal and said signal indicative of operand being present in said cache memory.

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