Logic circuit connecting input and output signal lines

• US 4,912,745 A
• Filed: 12/02/1988
• Issued: 03/27/1990
• Est. Priority Date: 05/19/1987
• Status: Expired due to Fees

• Current Assignee: Gazelle Microcircuits, Inc.
• Original Assignee: Gazelle Microcircuits, Inc.
• Inventors: Graham, Andrew C., Fitzpatrick, Mark E.
• Primary Examiner(s): Hudspeth, David
• Application Number:
  US07/278,876
• Time in Patent Office: 480 Days
• Field of Search: 307/446, 307/448, 307/450, 307/473, 307/475, 307/572, 307/574, 307/581, 307/443
• US Class Current: 326/117
• CPC Class Codes: H03K 19/018535 of Schottky barrier type [MESFET]
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state
• CPC Class Codes: H03K 19/0952 using Schottky type FET MESFETH03K19/09421, H03K19/09432, H03K19/096 take precedence
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Claims

1. A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:

first, second and third transistors;

said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal;

load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor;

said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;

said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal;

the control terminals of the first and third transistors being connected to the input signal lead;

the output signal lead being connected to the first current handling terminal of the third transistor; and

a load device connected between the respective current handling terminals of the first and third transistor and the second voltage supply terminal.

2. The structure as in claim 1, wherein the second voltage supply terminal is a ground voltage supply terminal.

3. The structure as in claim 1, wherein the load device is a diode forward biased in the direction from the first voltage supply terminal to the second voltage supply terminal.