Memory cell including single event upset rate reduction circuitry

• US 4,914,629 A
• Filed: 09/07/1988
• Issued: 04/03/1990
• Est. Priority Date: 09/07/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W., Blake, Terence G. W.
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US07/241,524
• Time in Patent Office: 573 Days
• Field of Search: 365/154, 365/156, 365/177
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

Claims

1. A bi-stable logic device comprising:

a set of cross-coupled inverters, said set of inverters including first and second inverters; and

a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first source/drain of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first source/drain of said first transistor.

2. A bi-stable logic device as recited in claim 1 wherein a second source/drain of said first transistor of said pair is connected to the input of said first inverter and wherein said first source/drain of said first transistor of said pair is connected to the output of said second inverter.

3. A bi-stable logic device as recited in claim 2 wherein said second source/drain of said second transistor of said pair is connected to said input of said second inverter and wherein said first source/drain of said second transistor of said pair is connected to said output of said first inverter.

4. A bi-stable logic device as recited in claim 1 wherein a second source/drain of said first transistor of said pair is connected to the output of said first inverter and wherein said first source/drain of said first transistor of said pair is connected to the input of said second inverter.

5. A bi-stable logic device as recited in claim 4 wherein a second source/drain of said second transistor is connected to said output of said second inverter and wherein said first source/drain of said second transistor of said pair is connected to said input of said first inverter.

6. A bi-stable logic device as recited in claim 1 wherein said field effect transistors are metal oxide semiconductor transistors.

7. A bi stable logic device as recited in claim 1 wherein each inverter includes a p-channel transistor and a n-channel transistor.