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Memory cell including single event upset rate reduction circuitry

  • US 4,914,629 A
  • Filed: 09/07/1988
  • Issued: 04/03/1990
  • Est. Priority Date: 09/07/1988
  • Status: Expired due to Term
First Claim
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1. A bi-stable logic device comprising:

  • a set of cross-coupled inverters, said set of inverters including first and second inverters; and

    a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first source/drain of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first source/drain of said first transistor.

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