High frequency anti-jam communication system terminal

• US 4,914,699 A
• Filed: 10/11/1988
• Issued: 04/03/1990
• Est. Priority Date: 10/11/1988
• Status: Expired due to Term

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: ITT Corporation (ITT, Inc.)
• Inventors: McCrady, Dennis, Dunn, James G., Lager, Bruce
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US07/256,342
• Time in Patent Office: 539 Days
• Field of Search: 380/34, 380/46, 375/1
• US Class Current: 380/34
• CPC Class Codes: H04B 1/69 Spread spectrum techniques
• CPC Class Codes: H04K 1/00 Secret communication
• CPC Class Codes: H04K 2203/16 for telephony
• CPC Class Codes: H04K 3/25 based on characteristics of target signal or of transmission as countermeasure against surveillance H04K3/827, e.g. using direct sequence spread spectrum or fast frequency hopping spread spectrum techniques H04B1/69

Abstract

There is disclosed a high frequency communication system of the type employing a high frequency terminal which terminal can transmit a processed signal in a transmitting mode or process a received signal in a receiving mode which terminal includes a first subsystem for voice processing, including a processor responsive to voice signals to provide a linear predictive coded voice signal at a given data rate which signal is coupled to a data modem subsystem that digitally encrypts said voice signal which data modem subsystem is coupled to a modem processor subsystem capable of processing said encrypted signal for providing frequency hopping, feedback equalization, intersymbol interference cancellation, error correction and interleaving to provide a transmitted signal which is relatively immune to jamming during said transmitting mode which includes a convolutional encoder means included in said modem processor subsystem responsive to said encrypted signal to provide a convoluted signal at a higher data rate than said encrypted signal at an output. There is an interleave buffer having an input coupled to said encoder outputs for interleaving said higher data rate signal according to an interleaving algorithm, a symbol encoder having one input responsive to said interleave signal and one input coupled to a source of PN training signals as stored to provide at an output an encoded signal encoded according to said PN signal which PN training signal differs for each transmitting frequency. This signal is then converted to an analog signal and eventually coupled to a transmitting means for transmitting said signal. The apparatus also contains receiver means which operate to employ improved equalization for a received signal according to said PN training signal blocks.

Claims

1. In a high frequency communication system employing a high frequency terminal which terminal can transmit a processed signal in a transmitting mode or process a received signal in a receiving mode, which terminal includes a first subsystem for voice processing including a processor responsive to voice signals to provide a linear predictative coded voice signal at a given data rate, which signal is coupled to a data modem subsystem to digitally encrypt said voice signal which data modem subsystem is coupled to a modem processor subsystem for processing said encrypted signal for providing frequency hopping, feedback equalization, intersymbol interference cancellation, error correction and interleaving to provide a transmitted signal which is relatively immune to jamming during said transmitting mode, the improvement therewith of apparatus for providing an improved transmitting operation comprising:

a convolutional encoder means included in said modem processor subsystem and responsive to said encrypted signal to provide a convoluted signal at a higher data rate than said encrypted signal at an output

an interleave buffer having an input coupled to said encoder output for interleaving said higher data rate signal according to an interleaving algorithm;

a symbol encoder having one input responsive to said interleaved signal and one input coupled to a source of PN training signals as stored to provide at an output an encoded signal encoded according to said PN signal which PN training signal differs for each transmitting frequency;

a transmitting filter means responsive to said encoded signal and operative to limit the bandwidth of said signal; and

a digital to analog converter means coupled to said transmitting filter means and operative to convert said limited bandwidth signal to an analog signal.

2. The apparatus according to claim 1 wherein said transmitting filter means includes a multiplier for multiplying said filtered signal by an exponential function and buffer means for storing said multiplied signal prior to application of said signal to said digital to analog converter means.

3. The apparatus according to claim 1 further including improved equalization means located in said modem processor subsystem and operative to improve equalization during said receiving mode, comprising in combination;

channel estimate means responsive to said PN training signal blocks to provide at an output an estimate of the received channel response;

said estimate implemented by a least squares algorithm means in response to said known block of training symbols to provide said estimate for a given received data block;

precancellation means responsive to said estimate for separating data into predetermined blocks of data;

matched filter means coupled to said precanceller means and responsive to said blocks for sampling said blocks of data at a given rate;

convolution means coupled to said matched filter means and having an output coupled to means for performing a long division to provide at said long division output means equalization to said data blocks according to ##EQU10## where G(z) is a feed forward equalizer transfer function and is a finite polynomial with K non zero coefficients;

C(z) is a finite polynomial with non zero coefficients;

M(z) is a finite polynomial and is the Z transform of the autocorrelation function of said estimated channel response.

4. The apparatus according to claim 3 wherein said estimated channel response is limited to M symbols and wherein M(z) has 2M-1 non-zero coefficients in the range of z.sup.(M-1) to z.sup.(M-1).

5. The apparatus according to claim 4 wherein C(z) has 2m-1 non zero coefficients in the range z^-(M-1) to z.sup.(M+K-2) where K is a constant.

6. The apparatus according to claim 3 wherein said correlation means includes canceller means for providing a recursion canceller polynomial according to:

##EQU11## where D_m (z) is an auxiliary polynomial. Initially, D₀ (z)=M(z), C₀ (z)=h₀ M(z) and h_o =1/M₀. Then the recursion is repeated for m=1, . . . , K-1 finally giving C(z)=C_K-1 (z).

7. The apparatus according to claim 6 wherein the following equations are also employed with said recursion:

##EQU12##

8. The apparatus according to claim 3 wherein said least squares algorithm means estimates said channel impulse response based on observations of said channel output in response to a known training data sequence according to ##EQU13## h'"'"'_j,=unknown channel response M=maximum number of symbols duration of the channel impulse response

N+M=number of training signals in a training block

9. The apparatus according to claim 8 including three sets of channel impulse responses for providing said response according to

h.sup.(0) =(h'"'"'₀,h'"'"'₃,h'"'"'₆, . . . )

h.sup.(1) =(h'"'"'₁,h'"'"'₄,h'"'"'₇, . . . )

h.sup.(2) =(h'"'"'₂,h'"'"'₅,h!₈, . . . )

10. The apparatus according to claim 1 further including a low data rate transmitting means located in said modem processor subsystem and operative to provide an input data rate of 400 bits per second,

encoding means including DFT means responsive to said input data to encode said data in the form of 6 bit groups and means for transmitting said 6 bit group at a different frequency rate.

11. The apparatus according to claim 10 including means operative in said transmitting mode to transmit a sequence of eight known PN training signals prior to transmitting data.

12. The apparatus according to claim 11 including means responsive in the receiving mode for receiving said PN symbols to provide therefrom a Doppler frequency estimate indicative of the quality of the transmission path.

13. The apparatus according to claim 12 including a low data rate receiving means located in said modem processor subsystem and including DFT means for measuring the amplitudes of received tones in a plurality of time slots,

Doppler connection means coupled to said DFT means to position said received tones in said slots according to the Doppler characteristics of said communications channel,

storage means for storing said received tones,

means coupled to said storage means to determine data boundaries for said received tones, and

decoder means coupled to said means for providing a decoded output signal.

14. The apparatus according to claim 12 wherein said DFT means is operative to generate 24 tone slots each spaced by 150 Hz.

15. The apparatus according to claim 12 further including tone map function means included in said DFT means for selecting 2 slots out of 12 slots which are used for a transmitted signal.

16. The apparatus according to claim 13 wherein said DFT means in said receiving means operates to measure amplitude of received tones in 12 tone slots.

17. The apparatus according to claim 16 including symbol detection means responsive to said 12 tone slots to measure the energy of said slots and to select 2 slots having the largest received energy.

18. The apparatus according to claim 13 including means for accumulating the squares of received sample energy within first and second time slots to provide an output timing error estimate indicative of the differences between received energy and means for storing said estimate wherein if said stored estimate is greater than a given number said first and second time slots are changed accordingly.

19. The apparatus according to claim 1 where said modem processor subsystem includes first and second processor modules with said first processor module coupled to said data modem subsystem and said second processor coupled to said first processor to exchange data and control information therewith.

20. The apparatus according to claim 3 wherein said modem processor subsystem includes analog to digital conversion means operative in said receiving mode to convert received analog data to digital data at an output.

21. The apparatus according to claim 20 wherein said analog to digital converter is sampled at a rate at least 3 times greater than said received data rate.