Structure for contacting devices in three dimensional circuitry

• US 4,914,739 A
• Filed: 05/25/1989
• Issued: 04/03/1990
• Est. Priority Date: 10/31/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder S.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US07/357,658
• Time in Patent Office: 313 Days
• Field of Search: 357/23.1, 357/23.4, 357/23.6, 357/41, 357/51, 357/55
• US Class Current: 257/302
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate. The described embodiment provides an electrical connection which facilitates the electrical characterization of the transistor and the capacitor by allowing separate connection to the transistor or the capacitor.

Claims

1. A semiconductor device for contacting integrated circuit components comprising:

a substrate including a trench therein, wherein said trench surrounds a portion of said substrate;

said substrate further including a surface;

said trench including trench sides and a trench bottom;

a capacitor formed within said trench out of direct contact with said surface;

a field effect transistor including a drain, source and gate, said drain and source including majority dopants of the same type;

said drain and source, both surrounding said trench, being situated substantially along said trench sides, and defining a channel region, along said trench sides, which surrounds said trench;

said source contacting said capacitor;

a well region of the same majority carrier type throughout for accessing said capacitor;

said well region being located within said portion of said substrate surrounded by said trench thereby allowing electrical access to said transistor and said capacitor for testing purposes.

2. A semiconductor device for contacting integrated circuit components comprising:

a substrate including a trench therein, wherein said trench surrounds a portion of said substrate;

said portion including a well region of the same majority carrier type throughout;

a first insulating layer substantially lining said trench;

a first conductive material positioned within said trench,

said first conductive material acting as a first capacitor plate of a capacitor including the substrate acting as a second capacitor plate and the insulating layer acting as a dielectric;

said trench being surrounded by trench sides;

a source, surrounding said trench, being situated substantially along said trench sides and contacting said first conductive material;

a drain, surrounding said trench, being situated substantially along said trench sides and being spaced from said source so as to define a channel region between said source and said drain, said drain and said source including majority dopants of the same type;

a second conductive material at least partially within said trench;

a second insulating layer between said first conductive material and said second conductive material;

said second conductive material acting as a gate of a field effect transistor including said drain and said source;

whereby said transistor and said capacitor can be accessed and thus tested through a circuit connection including said well region, said source, said channel and said drain.

3. A semiconductor device as recited in claim 2 wherein said first conductive material contacts said source through a polycrystalline silicon connection.

4. A semiconductor device as recited in claim 2 which further includes a third conductive material that contacts said drain so as to act as a bit line to the drain.

5. A semiconductor device as recited in claim 4 wherein said third conductive material contacts said drain through a polycrystalline silicon connection.