Semiconductor device with airbridge interconnection

• US 4,916,520 A
• Filed: 09/13/1988
• Issued: 04/10/1990
• Est. Priority Date: 09/24/1987
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kurashima, Yasumi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/243,974
• Time in Patent Office: 574 Days
• Field of Search: 357/71, 357/68, 357/65
• US Class Current: 257/776
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

There is disclosed a semiconductor device comprising a plurality of lower level interconnections having first, second and third lower level interconnections, an upper level interconnection connected to the first and second lower level interconnections and extending over the third lower level interconnection in spacing relationship, and at least one pier formed on a central portion of the upper surface of one of the first and second lower level interconnections, and the pier has a width less than that of aforesaid one of the first and second lower level interconnections and is covered in its entire surface with a film formed of the same material as of the upper level interconnection, so that a force applied for wafer separation is partially supported by the pier.

Claims

1. A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising:

(a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection;

(b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and

(c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection.

2. A semiconductor device as set forth in claim 1, in which a portion of said upper level interconnection over said third lower level interconnection is approximately equal in height to a portion of said film covering an upper surface of said pier.

3. A semiconductor device as set forth in claim 2, in which at least one of said lower level interconnections serves as a bonding pad which is kept idle in electrical operations.

4. A semiconductor device as set forth in claim 3, in which another pier is further formed on said bonding pad and has a width less than that of the aforesaid one of said first and second lower level interconnections so that the entire surface of said another pier is covered with a conductive strip, the portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said conductive strip covering an upper surface of said another pier.

5. A semiconductor device as set forth in claim 4, in which each pier is formed of polymide.

6. A semiconductor device fabricated on a semiconductor substrate overlain by a first insulating film, comprising:

(a) a plurality of lower level interconnections formed on said first insulating film, said lower level interconnections having first, second and third lower level interconnections, said first and second lower level interconnections being located on both sides of said third lower level interconnection;

(b) an upper level interconnection connected to said first and second lower level interconnections and extending over said third lower level interconnection, said upper level interconnection being spaced from said third lower level interconnection; and

(c) at least one pier formed on a central portion of an upper surface of one of said first and second lower level interconnections, said pier having a width less than that of the aforesaid one of the first and second lower level interconnections and being covered over its entire exposed surface with a film formed of the same material as of said upper level interconnection, a portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said film covering an upper surface of said pier, at least one of said lower level interconnections serving as a bonding pad which is kept idle in electrical operations, another pier being further formed on said bonding pad and having a width less than that of the aforesaid one of said first and second lower level interconnections so that the entire surface of said another pier is covered with a conductive strip, the portion of said upper level interconnection over said third lower level interconnection being approximately equal in height to a portion of said conductive strip covering an upper surface of said another pier, said semiconductor device being further provided with first and second pillow strips buried under aforesaid one of said first and second lower level interconnections and said bonding pad, respectively, the portion of said upper level interconnection over said third lower level interconnection being lower than the portion of said film covering the upper surface of said pier and the portion of said conductive strip.