Logic path length reduction using boolean minimization

• US 4,916,627 A
• Filed: 12/02/1987
• Issued: 04/10/1990
• Est. Priority Date: 12/02/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hathaway, David J.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/127,323
• Time in Patent Office: 860 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300, 364/578
• US Class Current: 716/103
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

Claims

1. A method for reducing a logic network to a specified number of gate levels, the logic network having a plurality of gates, a number of gate levels, at least one input, at least one output, and at least one worst path which represents a path through the logic network having at least as many gate levels as any other path through the logic network, the method comprising the steps of:

receiving data representing the topology of the logic network;

levelizing the gates of the logic network in a forward and a backward direction;

determining all of the gates of the logic network which are in the at least one worst path;

specifying a scoring function;

selecting, in accordance with the scoring function, one of the gates in the at least one worst path;

applying a local Boolean compression to the selected gate, thereby producing a compressed logic network having fewer gate levels than the number of gate levels of the logic network prior to compression;

comparing the number of gate levels of the compressed logic network with the specified number of gate levels; and

if the compressed logic network has a number of gate levels which is greater than the specified number of gate levels, then

repeating said levelizing, determining, specifying, selecting, applying, and comparing steps on the compressed logic network until the specified number of gate levels is achieved.

2. The method according to claim 1, wherein the selected gate is at least two levels from the at least one input and at least one level from the at least one output.

3. The method according to claim 1, further comprising the step of:

determining those gates of the logic network in a long path which represents a path through the logic network having more than the specified number of gate levels.

4. The method according to claim 1, further comprising the step of:

calculating for each of the gates a long path convergence factor which represents a number of paths through the logic network having more than the specified number of gate levels which converge at a particular gate.

5. The method according to claim 1, further comprising the steps of:

determining for each of the gates of the logic network an arrival time which represents the maximum path length from the at least one input to a particular gate; and

determining for each of the gates of the logic network a required time which represents the minimum path length from the at least one output to a particular gate.

6. The method according to claim 5, further comprising the step of:

calculating for each of the gates of the logic network a slack value which represents a difference between the required time and the arrival time.

7. The method according to claim 1, further comprising:

calculating for each of the gates a worst path convergence factor which represents a number of worst paths which converge at a particular gate.

8. The method according to claim 7, further comprising the step of:

applying a trial local Boolean compression on those gates of the logic network having a worst path convergence factor greater than zero and which are at least two levels from the at least one input and at least one level from the at least one output.

9. The method according to claim 8, further comprising the step of:

calculating a gate count increase value which represents a number of gates added to the logic network after said trial local Boolean compression is applied.

10. The method according to claim 8, further comprising the step of:

calculating a connection count increase value which represents a number of input connections added to the logic network after said trial Boolean compression step is applied.

11. A method for reducing a logic network to a specified number of gate levels, the logic network having a plurality of gates, a number of gate levels, at least one input, at least one output, and at least one worst path which represents a path through the logic network having at least as many gate levels as any other path through the logic network, the method comprising the steps of:

receiving data representing the topology of the logic network;

levelizing the gates in a forward and backward direction;

calculating for each of the gates a worst path convergence factor which represents a number of worst paths which converge at a particular gate;

calculating for each of the gates a long path convergence value which represents a number of paths through the logic network having more than the specified number of gate levels which converge at a particular gate;

applying a trial local Boolean compression on those gates of the logic network having a worst path convergence factor greater than zero and which are at least two levels from the at least one input and at least one level from the at least one output;

calculating a gate count increase value which represents a number of gates added to the logic network after said trial local Boolean compression is applied;

calculating a connection count increase value which represents a number of input connections added to the logic network after said trial Boolean compression is applied;

specifying a scoring function;

selecting, in accordance with the scoring function, one of the gates in the at least one worst path;

applying a local Boolean compression to the selected gate, thereby producing a compressed logic network having fewer gate levels than the number of gate levels of the logic network prior to compression;

comparing the number of gate levels of the compressed logic network with the specified number of gate levels; and

if the compressed logic network has a number of gate levels which is greater than the specified number of gate levels, than

repeating said levelizing, worst path convergence factor calculating, long path convergence value calculating, trial Boolean compression applying, gate count increase calculating, connection count increase calculating, specifying, selecting, local Boolean compression applying, and comparing steps on the compressed logic network until the specified number of gate levels is achieved.

12. The method according to claim 11, wherein said scoring function is a function of at least one of the worst path convergence factor, gate count increase value, the long path convergence factor, and the connection count increase value.

13. The method according to claim 11, further comprising the steps of:

determining for each of the gates of the logic network an arrival time which represents the maximum path length from the at least one input to a particular gate; and

determining for each of the gates of the logic network, a required time which represents the minimum path from the at least one output to a particular gate.

14. The method according to claim 13, further comprising the step of:

calculating for each of the gates a slack value which represents the difference of the required time minus the arrival time.

15. The method according to claim 14, wherein those gates having the most negative slack values are in worst path.

16. The method according tro claim 15, wherein those gates having negative slack values which are more positive than the most negative slack values are in long paths.