Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures

• US 4,916,652 A
• Filed: 09/30/1987
• Issued: 04/10/1990
• Est. Priority Date: 09/30/1987
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schwarz, Eric M., Vassiliadis, Stamatis
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/102,985
• Time in Patent Office: 923 Days
• Field of Search: 364/200, 364/736, 364/748, 364/900, 364/231.8
• US Class Current: 708/510
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the oldest instruction in the pipeline processor should complete, execution of the oldest instruction in such processor completes, leaving room for insertion of the particular instruction therein for execution. When the particular instruction is transmitted to its associated pipeline processor, information including the pipe number is stored in the dynamic history table for future reference.

Claims

1. A pipelined processing apparatus having a plurality of pipelined processors accomodating different types of instructions, comprising:

receiving means for receiving incoming instructions, which receiving means includes decode means for decoding each of the incoming instructions thereby identifying a category type for said each of the incoming instructions;

a plurality of pipelined processors each connected to said receiving means for temporarily holding at least some of the incoming instructions for execution, each pipelined processor being identified by a unique number;

switch means connected to said receiving means and coupled to said plurality of pipelined processors, said switch means changing to a standard single pipelining mode for a first category of instructions identified by said decode means and changing to a dynamic multiple pipelining mode for a second category of instructions identified by said decode means, with each instruction in said second category of instructions having the unique number for the pipelined processor which accomodates that type of instruction;

table means connected to the plurality of pipelined processors and to the receiving means for recording the numbers of one or more pipelined processor means in which said at least some of the incoming instructions are temporarily held for execution, and for controlling the completion of instruction processing by the plurality of pipelined processors so that such completion will be in a predetermined sequence; and

wherein said receiving means determines if a particular one of the pipelined processors is available for use, said receiving means inserting an incoming instruction in said particular one of the pipelined processors for execution when said particular one of the pipelined processors becomes available for use.

2. The apparatus of claim 1 wherein said first category of instructions which are processed in a standard single pipelining mode includes instructions having a length outside a predetermined range of bits or instructions which are more difficult to execute such as divides and square roots.

3. The apparatus of claim 1 which further includes hazard circuit means interconnected between said receiving means, said table means and said plurality of pipelining processors, for detecting data dependent hazards as well as collision hazards and for generating control signals to either allow or alternatively prevent execution of an instruction by one of the pipelined processors.

4. The apparatus of claim 1, wherein said particular one of the pipelined processors is available for use when the particular pipelined processor is not full of instructions of when, if the particular pipelined processor is full of instructions, the number of the particular pipelined processor matches one of the numbers recorded in the table means and, if the numbers match, the oldest one of said instructions in said particular pipelined processor has been executed.

5. The apparatus of claim 1, wherein said receiving means records the number of said particular one of the pipelined processors in said table means when said receiving means inserts said particular incoming instruction in said particular one of the pipelined processors for execution.

6. The apparatus of claim 1, wherein said receiving means comprises stacking means for stacking at least one of the incoming instructions.

7. The apparatus of claim 6, wherein said receiving means comprises decode means connected to the stacking means for decoding the oldest one of the stacked incoming instructions thereby producing a decoded output signal.

8. The apparatus of claim 7, wherein said receiving means comprises handshake means responsive to the decoded output signal of said decode means for developing a valid instruction signal and an acknowledge signal if said oldest one of the stacked incoming instructions is valid.

9. The apparatus of claim 8, wherein said receiving means comprises selection means responsive to said decoded output signal, said acknowledge signal, and said valid instruction signal for identifying and selecting a particular one of the plurality of pipelined processor means in accordance with said decoded output signal, said valid instruction signal, and said acknowledge signal and for passing certain characteristics of said oldest one of the stacked incoming instructions to the selected particular one of the plurality of pipelined processor means when the particular pipelined processor means is selected.

10. The apparatus of claim 6, wherein said stacking means comprises first stacking means for stacking at least two of the incoming instructions and second stacking means for also stacking said at least two of the incoming instructions, said second stacking means storing the numbers of the pipelined processor means in which said at least two of the incoming instructions are held for execution.

11. The apparatus of claim 10, further comprising:

data receiving means for receiving incoming data corresponding to said incoming instructions, said data receiving means including third stacking means for stacking the incoming data.

12. The apparatus of claim 11, wherein the instructions stacked in said second stacking means correspond, respectively, to the data stacked in said third stacking means whereby the oldest one of the instructions stacked in said second stacking means is executed in conjunction with corresponding data stacked in said third stacking means.

13. The apparatus of claim 12, wherein said oldest one of the instructions stacked in said second stacking means is also being held in one of said plurality of pipelined processor means, said corresponding data being transmitted to said one of said plurality of pipelined processor means for association with said oldest one of the instructions in accordance with the number of said one of said plurality of pipelined processor means stored in said second stacking means.

14. In an apparatus including an instruction receiving means for receiving instructions, a plurality of pipelined processor means, each pipelined processor means including internal pipe controls, a table means connected to the instruction receiving means and the plurality of pipelined processor means, and data receiving means for receiving data corresponding to the received instructions, a method of inserting a received instruction received via the instruction receiving means into one of the pipelined processor means and for associating a corresponding received data received via said data receiving means with said received instruction in said one of the pipelined processor means, comprising the steps of:

identifying said received instruction thereby determining the identity of said one of the pipelined processor means from among said plurality of pipelined processor means;

consulting said table means and the internal pipe controls associated with said one of the pipelined processor means to determine if said one of the pipelined processor means is ready for receipt of said received instruction and said corresponding received data;

stacking said instructions received via said instruction receiving means, including said received instruction, in an instruction stacking means, each instruction in each stack of the instruction stacking means including a number identifying one of the pipelined processors;

separately stacking said data received via said data receiving means, including said corresponding received data, in a data stacking means, there being a one-to-one correspondence between the stacked instructions and the stacked data; and

transmitting said received instruction and said corresponding received data from said instruction receiving means and said data stacking means to said one of the pipelined processor means identified in accordance with the number associated with said received instruction stored in said instruction stacking means when said one of the pipelined processor means is ready for receipt of said received instruction and said corresponding received data.

15. The method of claim 14, further comprising the step of storing in said table means the numbers of said plurality of pipelined processor means which previously received an instruction and its corresponding data, and wherein said consulting step includes searching said table means to determine if the number of said one of the pipelined processor means is recorded in said table means.

16. The method of claim 15, wherein said searching step includes determining if said number is located in a certain position in said table means indicating the oldest entry in said table means.

17. The method of claim 16, wherein after the searching step, if the number of said one of said plurality of pipelined processor means associated with said received instruction is recorded in said certain position in said table means, checking said one of said plurality of pipelined circuit means to determine if the oldest one of said previously received instructions has been fully executed to completion, and if so, allowing it to exit said one of said plurality of pipelined processor means, whereby if the oldest previously received instruction is processed to completion and is allowed to exit, the transmitting step to said one pipelined processor means can be performed for another of said received instructions and its corresponding data.