Single instruction multiple data (SIMD) cellular array processing apparatus employing multiple state logic for coupling to data buses

• US 4,916,657 A
• Filed: 12/12/1985
• Issued: 04/10/1990
• Est. Priority Date: 12/12/1985
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Inventors: Morton, Steven G.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/808,315
• Time in Patent Office: 1,580 Days
• Field of Search: 364/900, 364/200
• US Class Current: 712/22
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G06F 11/2051 in regular structures
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels. The data bus couplers may be associated with pins organized in a regular architecture and used in connection with bedirectional transceivers to multiplex data corresponding to a multiplicity of external buses onto the internal bus and vice versa. Using this pin architecture the data bus couplers may be dynamically configured to support a collection of two-level and four-level external buses to suit the interfacing needs of the chip.

Claims

1. In a cellular array of the type adapted to be connected to similar arrays via external buses and employing a plurality of processor cells arranged in an array of columns and rows, with said cells communicating with one another via a common bus having a plurality of parallel data lines, the combination therewith of an interface for receiving a multi-level logic signal from a single terminal of an external bus and for providing a plurality of data bits to parallel data lines of said common bus, said interface comprising:

logic level converting means, coupled between said terminal and said common bus, for receiving said multi-level logic signal from said terminal and in response thereto for providing first and second binary data bits to data lines of said common bus in accordance with the level of the multi-level logic signal from said single terminal, whereby a multi-level logic signal applied to said single terminal is converted to first and second binary data bits provided on data lines of said common bus.

2. The cellular array according to claim 1, wherein said converting means includes an analog-to-digital converter having an input terminal coupled to said single terminal and operative to provide at first and second outputs said first and second binary data bits according to the level of said logic signal.

3. The cellular array according to claim 2, further including selectable means, connected to said first and second ouputs, for directing said binary data bits to selected parallel data lines of the common bus.

4. The cellular array according to claim 3, wherein said logic level converting means is adapted to operate in a first mode when the multi-level logic signal is a four level logic signal and in a second mode when the logic signal is a two level logic signal and said selectable means includes a plurality of bidirectional gates for directing said first binary bit to a first of said parallel data lines and said second binary bit to a second of said parallel data lines in a first mode of operation, and for directing both said first and second binary bits to one of said first and second parallel data lines in a second mode of operation.

5. The cellular array according to claim 4, wherein said selectable means operated bidirectionally, directing binary bits both to and from said selected parallel data lines, in both said first and second modes of operation, said array further including:

a digital-to-analog converter having a first input coupled to said first output and a second input coupled to said second output, with the output of said digital-to-analog converter coupled to said single terminal for providing a signal level in accordance with binary data bits received at said first and second inputs; and

means for enabling one of said A/D and D/A converters in accordance with the direction of data flow.

6. The cellular array according to claim 4, further including means for selectively enabling said logic level converting means to select one of said first and second modes of operation.

7. In a cellular array of the type adapted to be connected in similar arrays via external buses and including a plurality of processing cells arranged an an array of columns and rows, with said cells communicating with one another via a common bus having parallel data lines, the combination therewith of an interface for providing a multi-level logic signal to a single terminal from parallel data lines of said common bus and for converting a multi-level logic signal from said single terminal to binary data bits for said common bus, comprising:

an analog-to-digital converter having an input coupled to said single terminal for providing at first and second outputs, binary bits according to the level of said multi-level logic signal on said terminal;

a digital-to-analog converter having an output coupled to said single terminal and having a first input coupled to said first output of said analog-to-digital converter and a second input coupled to the second output of said analog-to-digital converter to provide at the output of said digital-to-analog converter a different signal level for each binary combination of bits applied to said input terminals; and

means coupled to said converters to selectively enable one or the other according to whether data is being transmitted to or received from said terminal.

8. The cellular array according to claim 7, further including level shifting means coupled to said inputs of said digital-to-analog converter and therefore coupled to said outputs of said analog-to-digital converter.

9. The cellular array according to claim 7, further including a two-or-four level selector means disposed between said first and second outputs of said A/D converter and first and second data lines of the common bus for bidirectionally directing data bits between said first and second outputs and said first and second data lines respectively in a first mode of operation and between one of said first and second data lines and both said first and second outputs in a second mode of operation.

10. The cellular array processor as claimed in claim 9, further comprising:

means for selecting one of said first and second modes of operation.

11. In a cellular array chip of the type employing a plurality of processor cells arranged in an array and capable of communicating with one another via a common bus having parallel binary data lines, said cellular array chip being adapted to be connected to a plurality of external buses having parallel data lines, the combination therewith of a data bus coupler for allowing the use of multiple level logic on said external buses, said data bus coupler comprising:

means for connecting to two of the data lines of the common bus;

means for connecting to one data line of an external bus;

first means connected to said external bus connecting means for receiving multiple level logic data from said external bus and for providing two binary data outputs;

second means, connected to said two binary data outputs of the first means, for receiving two binary data bits and in response thereto providing a data output, said data ouput being connected to the external bus connecting means; and

bidirectional logic level selector means having a first pair of terminals connected to the two binary data outputs of the first means and a second pair of terminals connected to said common bus connecting means for connection to two data lines of the common bus, said logic level selector means being operative to bidirectionally pass data between the two binary data outputs and the two data lines of the common bus in a first mode of operation and to pass data between one of said two data lines of the common bus and both of said binary data outputs in a second mode of operation.

12. A cellular array as described in claim 11, including means for selectively enabling said first or second means in accordance with the desired direction of data flow.

13. A cellular array as described in claim 11, additionally comprising means for selecting one of said first and second modes of operation.

14. A cellular array as described in claim 11, wherein an external bus has one half the number of data lines as does the common bus and said array includes a plurality of data bus couplers equal in number to the number of data lines on said external bus, said data bus couplers each being connected to a pair of adjacent data lines of said common bus and to one data line of said external bus, so that when said data bus couplers are operated in the first mode of operation binary data on the common bus can be transmitted as four-level logic data on the external bus and vice versa.

15. A cellular array as described in claim 11, wherein said common bus carries first and second sets of binary data and a data bus coupler is provided for each data line of an external bus, said data bus couplers being numbered and arranged in pairs of adjacent odd and even numbered couplers, said cellular array additionally comprising a bidirectional transceiver means for each data bus coupler, said transceiver means being arranged in pairs associated with the pairs of data bus couplers and being disposed between the common bus connecting means of the data bus couplers and the data lines of the common bus, each said common bus connecting means having an even terminal and an odd terminal, each of said bidirectional transceiver means having a terminal connected to a data line of said common bus, each said bidirectional transceiver means additionally including first and second terminals, the first and second terminals of the even numbered transceiver means of each pair of transceiver means being connected to an even terminal of the common bus connecting means of the associated pair of data bus couplers, the first and second terminals of the odd numbered transceiver means of each pair being connected to an odd terminal of the common bus connecting means of the associated pair of data bus couplers, whereby each external bus connecting means of the even numbered data bus couplers provides two consecutive binary bits of the first set of data as one four-level logic bit and each external bus connecting means of the odd numbered data bus couplers provides two consecutive binary bits of the second set of data carried on said common bus as one four-level logic bit when said data bus couplers are operating in the first mode of operation and in a second mode of operation only the first set of data from the common bus is provided by the external bus connecting means with the data on the even data lines of said common bus being provided on the even data lines of the external bus and data on the odd data lines of said common bus being provided on the odd data lines of the external bus.