Semiconductor memory device having function of generating write signal internally

• US 4,916,670 A
• Filed: 01/31/1989
• Issued: 04/10/1990
• Est. Priority Date: 02/02/1988
• Status: Expired due to Term

• Current Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Atsushi, Kobayashi, Kazuya
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/304,318
• Time in Patent Office: 434 Days
• Field of Search: 365/233, 365/189.01, 365/189.04, 365/230.06, 365/230.08
• US Class Current: 365/233.1
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory device includes: a circuit for defining a cycle in response to a clock and a write enable signal and outputting a write control signal under a specific condition; a unit for inverting the clock to an inverted clock; a circuit for generating a write signal in response to the inverted clock when the write control signal is output; and a memory cell array in which a write access of data is carried out based on the write signal. Where a latch circuit is further provided which latches the write data and transmits the write data to the memory cell array in response to the clock or inverted clock and the write signal, an input terminal and an output terminal can be made common by making a latch timing of the write data different from that of the write enable signal, or the number of input terminals can be decreased by inputting the write data in a time sharing mode. This results in a decrease in scale of the whole circuit as a device. Also, by latching the write enable signal at a change in level of the clock and controlling a generation of the write signal or a prohibition of the generation at a reverse change in level thereof based on a control signal, a write operation can be cancelled, when necessary, with respect to a cell even if an address access to the cell is carried out.

Claims

1. A semiconductor memory device receiving an external clock having a rising edge and a falling edge comprising:

a memory cell array,

a first latch circuit operatively connected to said memory cell array, for receiving a control signal designating one of a read cycle and a write cycle for said memory cell array, said first latch circuit latching said control signal in response to one of the rising edge and the falling edge of said external clock;

a second latch circuit operatively connected to said memory cell array, for receiving a write data, said second latch circuit latching said write data in response to another of the rising edge and the falling edge of said external clock; and

a write signal generating circuit operatively connected to said memory cell array and said first latch circuit, for feeding a write signal to said memory cell array when said control signal latched in said first latch circuit designates said write cycle.

2. A device as set forth in claim 1, wherein said write signal generating circuit receives a write control signal designating a cancellation of a write operation at said another of the rising edge and the falling edge of said external clock and stops feeding said write signal to said memory cell array.

3. A semiconductor memory device comprising:

a cycle defining circuit for defining a read cycle and a write cycle in response to an external clock and an external write enable signal and outputting a read control signal or a write control signal based on a certain kind of defined cycle;

means for inverting said clock to an inverted clock;

a write signal generating circuit operatively connected to said cycle defining circuit, for generating a write signal in response to said inverted clock when said write control signal is output;

a memory cell array in which a read access or write access of data is carried out based on said read control signal or said write signal; and

a latch circuit operatively connected to said write signal generating circuit, for latching a write data and transmitting said write data to said memory cell array in response to said inverted clock and said write signal, whereby said write enable signal is latched at a change in level of said external clock in said write cycle and said write data is latched at a reverse change in level thereof.

4. A device as set forth in claim 3, wherein said cycle defining circuit includes a first register for latching and outputting said write enable signal in response to said external clock and a gate circuit for outputting said read control signal or said write control signal in accordance with a logical level of said write enable signal in a selected state of said device.

5. A device as set forth in claim 4, wherein said first register latches said write enable signal at a fall of said external clock and outputs said write enable signal at a rise thereof.

6. A device as set forth in claim 4, wherein said latch circuit includes a second register for latching and outputting said write data in response to said inverted clock and a buffer for transmitting said write data to said memory cell array in response to said write signal.

7. A device as set forth in claim 6, wherein said second register latches said write data at a rise of said inverted clock and outputs said write data at a fall thereof.

8. A semiconductor memory device comprising:

a cycle defining circuit for defining a cycle for carrying out a predetermined function in response to an external clock and an external write enable signal and outputting a write control signal in response to an external control signal in the defined cycle;

means for inverting said clock to an inverted clock;

a write signal generating circuit operatively connected to said cycle defining circuit, for generating a write signal in response to said inverted clock when said write control signal is output; and

a memory cell array in which a write access of data is carried out based on said write signal, whereby said write enable signal is latched at a change in level of said external clock in said defined cycle, and a control of a generation of said write signal or a prohibition of said generation is carried out at a reverse change in level of said external clock in accordance with a logical level of said external control signal.

9. A device as set forth in claim 8, wherein said external control signal is identical to said write enable signal.

10. A device as set forth in claim 9, wherein said cycle defining circuit includes a first register for latching and outputting said write enable signal in response to said external clock, a second register for latching and outputting said write enable signal in response to said inverted clock, and a gate circuit for effecting a generation of said write control signal or a prohibition of said generation in accordance with a logical level of said write enable signal in a selected state of said device.

11. A device as set forth in claim 10, wherein said first register latches said write enable signal at a fall of said external clock and outputs said write enable signal at a rise thereof, and said second register latches said write enable signal at a rise of said inverted clock and outputs said write enable signal at a fall thereof.

12. A device as set forth in claim 10, further comprising a third register for latching and outputting said write data in response to said inverted clock and a buffer for transmitting said write data to said memory cell array in response to said write signal.

13. A device as set forth in claim 12, wherein said third register latches said write data at a rise of said inverted clock and outputs said write data at a fall thereof.

14. A device as set forth in claim 8, wherein said external control signal is an asynchronous chip select signal irrelevant to said external clock.

15. A device as set forth in claim 14, wherein said cycle defining circuit includes a first register for latching and outputting said write enable signal in response to said external clock and a gate circuit for effecting a generation of said write control signal or a prohibition of said generation in accordance with a logical level of said write enable signal in a selected state of said device.

16. A device as set forth in claim 15, wherein said first register latches said write enable signal at a fall of said external clock and outputs said write enable signal at a rise thereof.

17. A device as set forth in claim 15, further comprising a second register for latching and outputting said write data in response to said inverted clock and a buffer for transmitting said write data to said memory cell array in response to said write signal.

18. A device as set forth in claim 17, wherein said second register latches said write data at a rise of said inverted clock and outputs said write data at a fall thereof.

19. A semiconductor memory device comprising:

a cycle defining circuit for defining a cycle for carrying out a predetermined function in response to an external clock and an external write enable signal, and outputting a write control signal based on a logical level of said write enable signal at the beginning of the defined cycle;

means for inverting said clock to an inverted clock;

a write signal generating circuit operatively connected to said cycle defining circuit, for generating a write signal in response to said inverted clock when said write control signal is output;

a memory cell array in which a write access of data is carried out based on said write signal; and

a latch circuit operatively connected to said write signal generating circuit, for latching a write data in response to either said external clock or said inverted clock and transmitting said write data to said memory cell array in response to said write signal, said write data being composed of a plurality of data and input in a time sharing mode, whereby a first half of said plurality of data is latched at a change in level of said external clock in said defined cycle and a second half thereof is latched at a reverse change in level thereof, and said plurality of data are simultaneously written in said memory cell array.

20. A device as set forth in claim 19, wherein said cycle defining circuit includes a first register for latching said write enable signal at a fall of said external clock and outputting said write enable signal at a rise thereof, and a gate circuit for outputting said write control signal when said write enable signal is at a predetermined logical level in a selected state of said device.

21. A device as set forth in claim 20, wherein said latch circuit comprises a pair of registers for latching and outputting said write data in response to said external clock and said inverted clock, respectively, and a corresponding pair of buffers for transmitting said write data to said memory cell array in response to said write signal.

22. A device as set forth in claim 21, wherein one of said pair of registers latches said write data at a fall of said external clock and outputs said write data at a rise thereof, and another register latches said write data at a rise of said inverted clock and outputs said write data at a fall thereof.