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Semiconductor memory device having function of generating write signal internally

  • US 4,916,670 A
  • Filed: 01/31/1989
  • Issued: 04/10/1990
  • Est. Priority Date: 02/02/1988
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device receiving an external clock having a rising edge and a falling edge comprising:

  • a memory cell array,a first latch circuit operatively connected to said memory cell array, for receiving a control signal designating one of a read cycle and a write cycle for said memory cell array, said first latch circuit latching said control signal in response to one of the rising edge and the falling edge of said external clock;

    a second latch circuit operatively connected to said memory cell array, for receiving a write data, said second latch circuit latching said write data in response to another of the rising edge and the falling edge of said external clock; and

    a write signal generating circuit operatively connected to said memory cell array and said first latch circuit, for feeding a write signal to said memory cell array when said control signal latched in said first latch circuit designates said write cycle.

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