Image processing system
First Claim
Patent Images
1. An image processing system comprising:
- image data input means for inputting image data;
memory means for storing image data input from said image data input means;
clock signal generating means for generating a clock signal which serves as a reference clock signal for writing image data in said memory means;
dividing means for dividing a clock signal from said clock signal generating means to produce a divided clock signal corresponding to a magnification factor; and
control means for controlling the writing of image data in said memory means in response to the divided clock signal produced by said dividing means,wherein said dividing means comprises a counter for counting up to a number R+1 of clock pulses where R+1 is equal to an integer multiple of ten, and said dividing means divides a clock signal from said clock signal generating means into a divided clock signal having clock pulses of period ##EQU1## where S is a value set in accordance with the magnification factor.
0 Assignments
0 Petitions
Accused Products
Abstract
An image processing system has a line sensor for reading an image, a binarizing circuit for binarizing the read image data, a clock generator for generating a clock for transferring the image data, and a frequency changing circuit for changing the frequency of the clock from the clock generator using a decimal counter (e.g., a DRM) to allow image reproduction of any desired magnification factor without errors.
69 Citations
11 Claims
-
1. An image processing system comprising:
-
image data input means for inputting image data; memory means for storing image data input from said image data input means; clock signal generating means for generating a clock signal which serves as a reference clock signal for writing image data in said memory means; dividing means for dividing a clock signal from said clock signal generating means to produce a divided clock signal corresponding to a magnification factor; and control means for controlling the writing of image data in said memory means in response to the divided clock signal produced by said dividing means, wherein said dividing means comprises a counter for counting up to a number R+1 of clock pulses where R+1 is equal to an integer multiple of ten, and said dividing means divides a clock signal from said clock signal generating means into a divided clock signal having clock pulses of period ##EQU1## where S is a value set in accordance with the magnification factor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeCanon Kabushiki Kaisha (Canon Inc.)
-
Original AssigneeCanon Kabushiki Kaisha (Canon Inc.)
-
InventorsArimoto, Shinobu
-
Primary Examiner(s)Boudreau, Leo H.
-
Application NumberUS07/205,601Time in Patent Office669 DaysField of Search382/47, 340/731, 358/287US Class Current382/298CPC Class CodesH04N 1/3935 with modification of image ...H04N 1/40068 Modification of image resol...
