Capacitor coupled push pull logic circuit

• US 4,918,336 A
• Filed: 12/02/1988
• Issued: 04/17/1990
• Est. Priority Date: 05/19/1987
• Status: Expired due to Term

• Current Assignee: Gazelle Microcircuits, Inc.
• Original Assignee: Gazelle Microcircuits, Inc.
• Inventors: Graham, Andrew C., Fitzpatrick, Mark E.
• Primary Examiner(s): Hudspeth, David
• Application Number:
  US07/279,183
• Time in Patent Office: 501 Days
• Field of Search: 307/443, 307/446, 307/448, 307/450, 307/475, 307/572, 307/574, 307/581, 307/246
• US Class Current: 326/117
• CPC Class Codes: H03K 19/018535 of Schottky barrier type [MESFET]
• CPC Class Codes: H03K 19/0952 using Schottky type FET MESFETH03K19/09421, H03K19/09432, H03K19/096 take precedence

Abstract

This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.

Claims

1. A buffer circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:

first, second and third transistors;

said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to the second voltage supply terminal;

load means connecting the first voltage supply terminal and first current handling terminal of the first transistor;

said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;

said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal connected to the second voltage supply terminal;

the control terminals of the first and third transistors being connected to the input signal lead;

a capacitor having a pair of terminals, one terminal connected to the first current handling terminal of the third transistor, and the other terminal connected to the output signal lead; and

a load device coupled between the respective second current handling terminals of the first and third transistors and the second voltage supply terminal.

2. The structure as in claim 1 and further comprising a load device connected between the one terminal of the capacitor and the output signal lead, in parallel with the capacitor.

3. The structure of claim 1 and further comprising a third voltage supply terminal, and a load device as part of the connection between the third voltage supply terminal and output signal lead.

4. A buffer circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:

first, second and third transistors;

said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal connected to said second voltage supply terminal;

load means connecting said first voltage supply terminal and said first current handling terminal of said first transistor;

said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;

said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal coupled to the second voltage supply terminal;

the control terminals of the first and third transistors being connected to the input signal lead;

a first load device connecting the first current handling terminal of the third transistor and the output signal lead; and

further comprising a second load device connected between the respective second current handling terminals of the first and third transistors, and the second voltage supply terminal.