Dynamic address mapping for conflict-free vector access

• US 4,918,600 A
• Filed: 08/01/1988
• Issued: 04/17/1990
• Est. Priority Date: 08/01/1988
• Status: Expired due to Fees

• Current Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Original Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Inventors: Harper, David T. III, Linebarger, Darel A.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/226,721
• Time in Patent Office: 624 Days
• Field of Search: 364/200, 364/300, 364/900
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

Conflict-free vector access of any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector. A respective storage scheme for each vector, for example, is selected to provide conflict-free access for a predetermined stride S. The respective storage scheme involves a rotation or permutation of an addressed row of corresponding memory locations in N parallel modules in main memory. The amount of rotation or permutation is a predetermined function of the predetermined stride S and the row address. The rotation is performed by modulo-N addition, or the permutation is performed by a set of exclusive-OR gates. For a system in which N is a power of 2 such that n=log₂ N, the predetermined stride S is factored into an odd component and an even component that is a power of 2. The factorization is easily performed by a shift and count procedure, a shifter and counter, or a priority encoder. The amount of rotation or permutation is a predetermined function of the even component and the row address, and is preferably obtained by selecting a field of the row address in accordance with the maximum of s and n, and masking the selected field with a mask generated from the minimum of s and n.

Claims

1. A method of dynamic address mapping for conflict-free vector access in a vector processing system having a processor accessing a main memory having a multiplicity of N memory modules in which sequential memory addresses are mapped to different ones of the memory modules, said processor including means for referencing successive addresses differing by a constant access stride, said method comprising the steps of:

(a) determining a stride S greater than 1 for which a vector is to be accessed;

(b) accessing said main memory to load data for said vector in said main memory using a storage scheme that is preselected for said vector and is a predetermined function of said stride S and permits conflict-free sequential access and conflict-free access with said stride S;

(c) accessing said main memory to access data for said vector by using the storage scheme preselected for said vector; and

(d) repeating steps (a), (b) and (c) for a multiplicity of different vectors, wherein different respective strides S are determined for the vectors, and said main memory is accessed using different respective storage schemes for said vectors, so that the storage scheme is selected dynamically for said multiplicity of vectors.

2. The method as claimed in claim 1, wherein said storage scheme is preselected by factoring said stride S into an odd component and an even component that is a power of 2, and preselecting said storage scheme as a predetermined function of said even component.

3. The method as claimed in claim 2, wherein said memory addresses include a module address field and a row address field, said row address field specifying a respective storage location in each memory module, and said preselected storage scheme is preselected by selecting a portion of said row address field as a predetermined function of said even component, and determining a module address as a predetermined function of said module address field and the selected portion said row address field.

4. The method as claimed in claim 3, wherein said module address is determined as an exclusive-OR function.

5. The method as claimed in claim 3, wherein said module address is determined as a modulo-N addition.

6. The method as claimed in claim 3, wherein said selecting of said portion of said row address field is performed by selecting a predetermined number of address bits and masking said predetermined number of bits with a mask generated as a predetermined function of said even component.

7. The method as claimed in claim 6, wherein said number N of modules is a power of 2 such that n=log₂ N, said selecting of a predetermined number of bits is controlled by the maximum of n and log₂ of said even component, and said mask is generated from the minimum of n and log₂ of said even component.

8. The method as claimed in claim 2, wherein said stride S is factored by loading a binary shift register, shifting said shift register, and counting how many times said shift register is shifted until a serial output of said shift register assumes a predetermined logic state.

9. The method as claimed in claim 1, wherein said memory addresses include a module address field and a row address field, said row address field specifying a respective storage location in each memory module, and said preselected storage scheme is preselected by selecting a portion of said row address field as a predetermined function of said stride S, and determining a module address as a predetermined function of said module address field and said selected portion of said row address field.

10. A method of mapping addresses in a vector processing system of the kind having a processor and a main memory including a plurality of N memory modules;

said processor supplying an address having a module address field, and a row address field selecting a respective storage location in each of said memory modules;

said processor also supplying a parameter for selecting storage schemes providing predetermined mappings of said address to said storage locations in said modules, said method comprising the steps of;

(a) selecting a portion of said row address field in response to said parameter, and

(b) determining a module address as a predetermined function of said module address field and the preselected portion of said row address field.

11. The method as claimed in claim 10, wherein said module address is determined by modulo-N addition of said module address field and the preselected portion of said row address field.

12. The method as claimed in claim 10, wherein said module address is determined by the exclusive-OR of said module address field and the preselected portion of said row address field.

13. The method as claimed in claim 10, wherein said step of selecting said portion of said row address field is performed by selecting a predetermined number of bits of said row address field in response to said parameter, and masking said predetermined number of bits by a mask generated as a predetermined function of said parameter.

14. The method as claimed in claim 13, wherein said predetermined number of bits of said row address field are selected in response to a maximum one of said parameter and a constant related to said number N of modules, and said mask is generated in response to a minimum one of said parameter and said constant.

15. An address mapping circuit for mapping an address from an address bus to physical storage locations in a plurality of N memory modules connected to said address mapping circuit, said address including a row address field specifying a respective address in each of said modules, and a module address field, said address mapping circuit including

(a) selecting means, connected to said address bus, for selecting a portion of said row address field in response to a predetermined parameter, and

(b) determining means, connected to said address bus, said selecting means and said plurality of N memory modules, for determining a module address as a predetermined function of said module address field and said portion of said row address field.

16. The address mapping circuit as claimed in claim 15, wherein said determining means includes adding means, connected to said address bus, said selecting means and said plurality of N memory modules, for performing a modulo-N addition of said module address field and said portion of said row address field to determine said module address.

17. The address mapping circuit as claimed in claim 15, wherein said determining means includes exclusive-OR means, connected to said address bus, said selecting means and said plurality of N memory modules, for performing an exclusive-OR of said module address field and said portion of said row address field.

18. The address mapping circuit as claimed in claim 15, wherein said selecting means for selecting said portion of said row address field includes mask generating means for generating a mask in response to said parameter, and means, connected to said mask generating means, said address bus and said determining means, for selecting and masking a predetermined number of bits of said row address field in response to said parameter and said mask to obtain said portion of said row address field.

19. The address mapping circuit as claimed in claim 18, wherein said means for selecting and masking said predetermined number of bits of said row address field includes bit selecting means, connected to said determining means, for selecting said bits in response to a maximum one of said parameter and a constant related to said number N of modules to obtain said portion of said row address field, and said means for generating said mask includes means, connected to said bit selecting means, for generating said mask in response to a minimum one of said parameter and said constant.

20. The address mapping circuit as claimed in claim 15, further comprising factoring means, connected to said selecting means, for generating said parameter by factoring a specified value into an odd component and a component that is a power of 2, and determining the log₂ of the component that is a power of 2.