Hierarchical floorplanner

• US 4,918,614 A
• Filed: 06/02/1987
• Issued: 04/17/1990
• Est. Priority Date: 06/02/1987
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Raam, Susan, Lai, Jiun-Hao, Modarres, Hossein
• Primary Examiner(s): Arnold, Bruce Y.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/057,843
• Time in Patent Office: 1,050 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/480
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A system in which logic and/or memory elements are automatically placed on an integrated circuit ("floorplanning") taking into account the constraints imposed by the logic designer, not only increase the density of the integrated circuit, and the likelihood of routing interconnections among the elements on that circuit, but it also enables the user to quickly modify the floorplan manually, and then graphically display the results of such modifications. By conforming itself to the logic designer'"'"'s modular, hierarchical design, the system is capable of placing elements at each level of the specified hierarchy, based upon the number of interconnections between elements throughout that hierarchy. The system includes means for estimating the size of elements which have not yet been laid out, and for partitioning groups of elements into successively smaller "slices" of the integrated circuit (using heuristic techniques when exhaustive methods are no longer feasible) until all elements are placed relative to one another. The system also includes means for determining the precise shapes of elements on the integrated circuit, based upon the relative placement of such elements, and upon the additional area required for routing interconnections among such elements. The functionality of this hierarchical floorplanning system can be embodied in the form of software, hardware or any combination thereof, because the system'"'"'s hierarchical methodology and structure is independent of its particular embodiment.

Claims

1. A method of making, including floorplanning functions for, an integrated circuit, said integrated circuit comprising a hierarchy of N level of functions,

where N is an integer (N≧

1) representing the number of hierarchical levels of functionality in the integrated circuit, the first of said levels representing the integrated circuit as a whole, and

where n is an integer (1≦

n≦

N) representing the level of any particular function in the hierarchy,

said hierarchy defining at least one of said (n)th level functions (a parent function) as a plurality of (n+1)st level functions (children functions, each being a child function),

each child function (which is not also a parent function) being a terminal function, each terminal function being connected to at least one other terminal function, by at least one net,

each net defining a plurality of interconnected terminal functions, comprising the steps of;

designing the integrated circuit,

estimating the number of connections between functions throughout all N levels of the hierarchy,

determining the location on the integrated circuit of each (n)th level function in the hierarchy, based in part upon said estimated number of connections, and

fabricating the integrated circuit having the location of each (n)th level function as determined in the previous step.

2. The method of claim 1 wherein the step of estimating the number of connections between functions throughout all N levels of the hierarchy comprises the steps of:

determining the expected number of connections between the terminal functions connected by each net, by dividing the minimum number of connections among said terminal functions by the total number of permutations of pairs of said terminal functions, and

determining the expected number of connections between each nonterminal function and all other functions in the hierarchy, by summing the expected number of connections between the terminal functions which are children functions of said nonterminal function and all the other terminal functions.

3. The method of claim 1 wherein the step of determining the location on the integrated circuit of each (n)th level function in the hierarchy comprises the step of determining the location on the integrated circuit of each child function in the hierarchy, such that said child function is placed in the area of the integrated circuit occupied by its parent function.

4. The method of claim 1 wherein the step of determining the location on the integrated circuit of each (n)th level function in the hierarchy comprises the step of:

determining the location of (n)th level children functions relative to one another within their parent, including

determining the location of 2d level children functions, relative to one another within their parent, based in part upon said estimated number of connections, and

determining the location of (n)th level children functions (n≧

3), relative to one another within their parent, based in part upon both said estimated number of connections and the location of (k)th level children functions (k≦

n), relative to one another within their parent.

5. The method of claim 4 wherein the step of determining the location of (n)th level children functions relative to one another within their parent comprises the steps of:

partitioning said children functions into two groups,

determining the location on the integrated circuit of each of said two groups relative to the other, and

successively partitioning each of said two groups of functions into two groups, and determining the location on the integrated circuit of each of said latter two groups relative to the other, until each of said groups contains exactly one function.

6. The method of claim 5 wherein the steps of partitioning said children functions into two groups and determining the location on the integrated circuit of each of said two groups relative to the other comprises the steps of:

dividing the parent function into two regions, such that each of said regions is either on top of, below, to the left of, or to the right of the other, each of said two regions comprising one of said two groups of functions,

calculating, for a plurality of the possible permutations of said functions between said two groups, the absolute value of the difference between the sum of the areas of the functions in one of said two groups and the sum of the areas of the functions in the other of said two groups, said absolute value divided by the sum of the areas of the functions in both of said groups (the proportional area difference),

using said estimated number of connections to calculate the number of connections between functions in one of said two groups and either functions in the other of said two groups or functions not in either of said two groups but on the same side of the line separating said two regions as is the other of said two groups, and

selecting said permutation of said functions between said two groups which yields the minimum sum of said proportional area difference and said number of connections between functions, thereby determining the location on the integrated circuit of each of said two groups relative to the other.

7. The method of claim 1 wherein the step of determining the location on the integrated circuit of each (n)th level function in the hierarchy comprises the steps of

defining a shape function, representing one or more possible shapes of each terminal function,

determining the shape function of each parent function by combining the shape functions of its children functions, thereby determining the shape function of the integrated circuit, and

selecting the shape of the integrated circuit, thereby determining the shape of each function on the integrated circuit.

8. The method of claim 7 wherein the step of determining the shape function of each parent function by combining the shape functions of its children functions comprises the steps of:

determining whether the location of each child function, relative to another of said child functions, is above, below, to the left of, or to the right of said other child function,

determining the X and Y coordinates of said parent'"'"'s shape function, for each of said child functions which is either above or below said other child function, by calculating, for each X coordinate corresponding to the X coordinates of said children functions, the sum of the Y coordinates of each of said children functions, and

determining the X and Y coordinates of said parent'"'"'s shape function, for each of said child functions which is either to the left or to the right of said other child function, by calculating, for each Y coordinate corresponding to the Y coordinates of said children functions, the sum of the X coordinates of each of said children functions.

9. The method of claim 1 wherein the step of determining the location on the integrated circuit of each (n)th level function in the hierarchy comprises the steps of

determining the locations of (n)th level functions relative to one another within their parent, including

determining the location of 2d level children functions, relative to one another within their parent, based in part upon said estimated number of connections, and

determining the location of (n)th level children functions (n≧

3), relative to one another within their parent, based in part upon both said estimated number of connections and the location of (k)th level children functions (k<

n), relative to one another within their parent, and

transforming said locations of (n)th level functions relative to one another within their parent into precise locations on the integrated circuit, including

defining a shape function, representing one or more possible shapes of each terminal function,

determining the shape function of each parent function by combining the shape functions of its children functions, thereby determining the shape function of the integrated circuit, and

selecting the shape of the integrated circuit, thereby determining the shape of each function on the integrated circuit.

10. The method of claim 9 wherein the step of determining the location on the integrated circuit of each (n)th level function in the hierarchy also comprises the steps of:

estimating, and allocating to the area occupied by each function, the routing area required to connect that function to other functions on the integrated circuit, and

repeating the step of transforming said locations of (n)th level functions relative to one another within their parent into precise locations on the integrated circuit, taking into account said routing area allocated to the area occupied by each function.

11. The method of claim 1 wherein the steps take into account all N levels of the hierarchy.

12. The method of claim 1, wherein some of the functions are psuedoterminal functions.

13. A method of making, including estimating the area occupied by (n)th level functions of, an integrated circuit, said integrated circuit comprising a hierarchy of N levels of functions,

where N is an integer (N≧

1) representing the number of hierarchical levels of functionality in the integrated circuit, the first of said levels representing the integrated circuit as a whole, and

where n is an integer (1≦

n≦

N) representing the level of any particular function in the hierarchy,

said hierarchy defining at least one of said (n)th level functions (a parent function) as a plurality of (n+1)st level functions (children functions, each being a child function),

each child function (which is not also a parent function) being a terminal function, each terminal function being connected to at least one other terminal function, by at least one net,

each net defining a plurality of interconnected terminal functions;

comprising the steps of;

designing the integrated circuit,

estimating the area of each terminal function which comprises many small cells the collective layout of which is not specified (macrocells), including estimating the number of tracks necessary to interconnect said macrocells,

determining the area of said terminal function of macrocells by adding, to the sum of the areas occupied by said macrocells, the product of said number of tracks and the known width of the average track,

estimating the area of each function which is not a terminal function, including

estimating the precentage of the total area of the integrated circuit available for routing connections among functions, and

distributing the available area uniformly to each parent function by summing the areas of each of its children functions, and multiplying that sum by said percentage, and

fabricating the integrated circuit having the area occupied by each function as determined in the prior steps.

14. The method of claim 13 wherein the step of estimating the number of tracks necessary to interconnect said macrocells comprises the steps of

raising the sum of the area occupied by said macrocells to a power equal to a first constant value, and

multiplying that sum raised to that power by a second constant value.

15. A system for making, including floorplanning functions for, an integrated circuit, said integrated circuit comprising a hierarchy of N levels of functions,

where N is an integer (N≧

1) representing the number of hierarchical levels of functionality in the integrated circuit, the first of said levels representing the integrated circuit as a whole, and

where n is an integer (1≦

n≦

N) representing the level of any particular function in the hierarchy;

said hierarchy defining at least one of said (n)th level functions (a parent function) as a plurality of (n+1)st level functions (children functions, each being a child function),

each child function (which is not also a parent function) being a terminal function, each terminal function being connected to at least one other terminal function, by at least one net,

each net defining a plurality of interconnected terminals functions,

comprising;

means for designing the integrated circuit,

means for determining the location of said integrated circuit of (n)th level children functions (n≧

2), relative to one another within their parent,

means for determining the shape of said (n)th level children functions, and

means for fabricating the integrated circuit with each function having the location and shape as determined in the previous steps.

16. The system of claim 15 also comprising:

means for calculating the additional area required to interconnect said (n)th level children functions, and

means for redetermining the shape of said (n)th level children functions, based in part upon said additional area.

17. The system of claim 15 also comprising means for graphically displaying the location on the integrated circuit of (n)th level functions.