Computer bus having page mode memory access

• US 4,918,645 A
• Filed: 09/17/1987
• Issued: 04/17/1990
• Est. Priority Date: 09/17/1987
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Wang Laboratories Incorporated
• Inventors: Lagoy, Brian E. J. Jr.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Richman, Glenn
• Application Number:
  US07/098,449
• Time in Patent Office: 943 Days
• Field of Search: 365/222, 371/13, 364/200 MS File, 364/900 MS File
• US Class Current: 711/151
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Method and apparatus are disclosed for use in a digital computer system having a system bus for interconnecting together various agents. A page mode type of memory access provides for the rapid transmission of a block of data across the bus. Blocked refresh circuitry is also employed which disables, if possible, the burst refresh of the memory until a data transfer is completed. A local processor upon an agent having a memory controlled in such manner is provided with a high priority signal line for overriding a current bus transfer for gaining access to the memory. During such a high priority access the blocked refresh circuitry operates in a manner somewhat similar to its operation during the sequential bus transfer, however fewer rows are refreshed during the burst refresh.

Claims

1. Memory control apparatus for use in a data processing system having at least a requesting agent and said replying agent electrically coupled together by a system bus, the requesting agent requesting access to a memory on the replying agent for storing and retrieving data therein over the system bus, the apparatus comprising:

means, associated with a replying agent, for detecting a request for initiating an access to a memory on the replying agent, the request detecting means being coupled to a system bus, and request being made over the system bus by a requesting agent;

means, responsive to the request detecting means detecting the request, for asserting a plurality of memory address control signals for accessing a plurality of times the memory on the replying agent, the control signals comprising at least a row address strobe signal associated with a memory row address and a column address strobe signal associated with a memory column address; and

means for detecting a completion of the access to the memory, the completion detecting means being responsive to an end of access control signal generated by the requesting agent, the access completion detecting means being coupled to the memory address control signal asserting means for halting the operation thereof after the end of access control signal is detected; and

wherein

the memory address control signal asserting means asserts the memory address control signals by asserting the row address strobe in conjunction with a row address being indicative of a page of data within the memory, and thereafter asserts and deasserts a plurality of times the column address strobe signal in conjunction with a plurality of column addresses for performing a page mode type of memory access.

2. The memory control apparatus of claim 1 and further comprising:

means for generating a memory refresh request signal at predetermined intervals;

means for counting each of the refresh request signals;

means, coupled to the refresh request signal counting means, for comparing a value of the counted refresh request signals to a predetermined threshold value and for determining when a number of counted refresh request signals equals or exceeds the predetermined threshold value; and

means, responsive to the comparing means determining that a number of counted refresh request signals at least equals the predetermined threshold value, for refreshing a plurality of memory rows, the number of memory rows being refreshed being substantially equal to the counted value.

3. The memory control apparatus of claim 2 wherein the memory row refreshing means is coupled to the memory address control signal asserting means and is responsive to an operation of the memory address control signal asserting means for disabling refreshing of the memory during the operation of the memory address control signal asserting means.

4. The memory control apparatus of claim 3 wherein the comparing means further comprises means for comparing the value of the counted signals to a predetermined maximum value for determining when a number of counted refresh request signals equals the predetermined maximum value, and wherein

the memory row refreshing means is further responsive to an operation of the maximum value comparing means for determining when the counted value equals the predetermined maximum value for suspending an operation of the memory address control signal asserting means and for refreshing a predetermined number of rows of the memory.

5. The memory control apparatus of claim 4 wherein the predetermined interval is approximately 13.8 microseconds, wherein the predetermined threshold value and the predetermined maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is an even number of rows.

6. The memory control apparatus of claim 1 and further comprising:

means for detecting a memory page boundary having inputs coupled to the memory column address and an output expressive of a state of the memory column address that is indicative of a memory page boundary; and

means, responsive to the output of the memory page boundary detecting means, for deasserting the row address strobe signal, providing a memory row address expressive of another page of data, and reasserting the row address strobe signal.

7. The memory control apparatus of claim 4 wherein the replying agent further has a local data processing means coupled to the memory and wherein the memory control apparatus further comprises:

means, responsive to an occurrence of a high priority memory access request from the local data processing means, for suspending an operation of the memory address control signal asserting means for accessing the memory in response to a request from the requesting agent; and

means, responsive to an occurrence of a high priority memory access request, for enabling the accessing of the memory by the local data processing means.

8. The memory control apparatus of claim 7 wherein the memory row refreshing means is coupled to the memory address control signal asserting means and is responsive to an occurrence of a high priority memory access request for disabling the refresh of the memory during an operation of the local data processing means access enabling means.

9. The memory control apparatus of claim 8 wherein the predetermined interval is approximately 13.8 microseconds, wherein the threshold value and the maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is two.

10. The memory control apparatus of claim 1 wherein said bus comprises three clock signal lines and wherein a first one of said clock signal lines has a first given frequency, a second one of said clock signal lines has a second given frequency substantially equal to two times said first given frequency and a third one of said clock signal lines has a third given frequency substantially equal to four times said first given frequency.

11. The memory control apparatus of claim 10 wherein said first given frequency is substantially equal to 5 MHZ.

12. A method for controlling a memory for use in a data processing system having at least a requesting agent and a replying agent electrically coupled together by a system bus, the requesting agent requesting access to a memory on the replying agent for storing and retrieving data therein over the system bus, the method comprising the steps of:

detecting a request from a requesting agent for initiating an access to said memory on a replying agent;

asserting a plurality of memory address control signals for accessing the memory on the replying agent, the control signals comprising at least a row address strobe signal associated with a memory row address and a column address strobe signal associated with a memory column address; and

detecting a logic state of an end of access system bus control signal that indicates a completion of the access to the memory; and

wherein

the step of asserting is accomplished by asserting the row address strobe signal in conjunction with a memory row address indicative of a page of data within the memory, and thereafter asserting and deasserting a plurality of times the column address strobe signal, in conjunction with a plurality of memory column addresses, for performing a page mode type of memory access.

13. The method of claim 12 and further comprising the steps of:

generating a memory refresh request signal at predetermined intervals;

counting each of the memory refresh request signals;

comparing a value of the counted memory refresh request signals to a predetermined threshold value for determining when a number of counted memory refresh request signals equals or exceeds the predetermined threshold value; and

refreshing a plurality of memory rows, a number of rows being refreshed being equal to the counted value of the memory refresh request signals.

14. The method of claim 13 and further comprising the step of suspending the step of refreshing a plurality of memory rows during a performance of the step of asserting.

15. The method of claim 14 wherein the step of comparing further comprises a step of:

comparing the value of the counted memory refresh request signals to a predetermined maximum value;

determining when the counted value of the memory refresh request signals equals the predetermined maximum value;

suspending the performance of the step of asserting; and

refreshing a predetermined number of rows of the memory.

16. The method of claim 15 wherein the predetermined interval is approximately 13.8 microseconds, wherein the threshold value and the predetermined maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is an even number of rows.

17. The method of claim 12 wherein step of asserting further comprises the steps of:

detecting a memory page boundary by monitoring the memory column address to detect a memory column address that is indicative of a memory page boundary;

deasserting the row address strobe signal;

providing a row address expressive of another page of data; and

reasserting the row address strobe.

18. The method of claim 15 wherein the replying agent has a local data processing means coupled to the memory and further comprising the step of, in response to a request from the local data processing means for access to the memory:

suspending the performance of the step of asserting; and

enabling the accessing of the memory for the local data processing means.

19. The method of claim 18 and further comprising the step of suspending the performance of the step of refreshing a plurality of memory rows during the step of enabling.

20. The method of claim 19 wherein the predetermined interval is approximately 13.8 microseconds, wherein the threshold value and the maximum value are 24 and 41, respectively, and wherein the predetermined number of rows is two.