Method of making ultra dense dram cells

• US 4,920,065 A
• Filed: 10/27/1989
• Issued: 04/24/1990
• Est. Priority Date: 10/31/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, Sang H., Chin, Daeje
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): THOMAS, TOM
• Application Number:
  US07/428,100
• Time in Patent Office: 179 Days
• Field of Search: 437/38, 437/47, 437/52, 437/60, 437/203, 437/228, 437/919, 156/463, 156/644, 357/23.6, 357/51, 365/188, 365/189
• US Class Current: 438/243
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells. Each gate in a conduit is disposed in insulated spaced relationship with a memory cell channel region which, in response to signals on the gate turns on a column of channel regions so as to permit the entry of charge into a selected storage region when a bitline associated with a particular cell is energized. The resulting array shows rows of pairs of memory cells wherein each cell of a pair is spaced from the other by a portion of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions of conductive material acting as a counterelectrode.

Claims

1. A process for fabricating an ultra dense DRAM memory array comprising the steps of:

forming a first plurality of trenches in a semiconductor substrate which is spaced from an underlying substrate by an insulating layer which extends through said semiconductor substrate and said insulating layer into said underlying substrate said trenches having a given depth and extending in a given direction,

refilling said plurality of trenches with an insulating material,

forming a second plurality of trenches in said semiconductor substrate through said semiconductor substrate and said insulating layer into said underlying substrate to said given depth leaving a plurality of active device regions and simultaneously excavating portions of said insulating material from said first plurality of trenches between said second plurality of trenches to a depth less than said given depth,

refilling said second plurality of trenches and said excavated portions of said first plurality of trenches with a conductive material, removing said conductive material from said excavated portions of said first plurality of trenches to expose the surfaces of said insulating material therein and from selected of said second plurality of said refilled trenches to a depth below said depth less than said given depth to form a plurality of flat topped regions of said conductive and said insulating materials which extend in a direction orthogonal to said given direction,

oxidizing said plurality of flat topped regions of conductive material such that the tops of the resulting insulating oxide are at the same level as the tops of said flat topped regions of insulating material forming a plurality of gate conduits extending in a direction orthogonal to said given direction,

forming a pair of conductive gate elements in each of said gate conduits each of said conductive gate elements being disposed in insulted spaced relationship with adjacent active device regions of said plurality of active device regions.

2. A process according to claim 1 further including the step of:

forming flat topped insulation in said gate conduits to electrically isolate each one of said pairs of conductive gate elements from each of the other of said pairs of conductive gates,

implanting said plurality of device regions with a conductivity type determining impurity to form a plurality of implanted device regions, and

depositing and patterning a plurality of conductive lines extending in said given direction each of which contacts a number of said plurality of implanted device regions.

3. A process for forming an ultra dense dynamic random access memory array comprising the steps of:

forming a first plurality of insulation filled trenches in a semiconductor substrate of first height,

forming a second plurality of trenches orthogonally with said first plurality of trenches in said substrate and in portions of said insulation filled trenches leaving a plurality of semiconductor regions of first height with gaps therebetween and a plurality of insulator regions of a second height less than said first height disposed between said insulator regions of said first height,

refilling said second plurality of trenches such that selected of said gaps are partially filled with conductive and insulating material in that order exposing portions of said semiconductor regions extending above said partially filled gaps, the latter having a height equal to said second height, and

forming a plurality of conductive gates orthogonal to said first plurality of trenches each said gate being disposed in insulated spaced relationship with a number of said exposed portions of said semiconductor regions and extending over said partially filled gaps and said insulator regions of said second height.

4. A process according to claim 3 further including the steps of

insulating adjacent gates from each other,

doping a portion of each portion of said semiconductor region extending above said partially filled gap to form a region of opposite conductivity type therein, and

forming a plurality of conductive interconnections each said interconnection being connected to a plurality of said opposite conductivity regions and extending in the same direction as said first plurality of trenches.

5. A process according to claim 3 wherein said substrate includes a first layer of semiconductor material of first conductivity type having a region of second conductivity type extending from its surface partially into said first layer, said first layer being disposed over a second layer of said first conductivity type and spaced from said first layer by a layer of insulating material.

6. A process according to claim 3 wherein said semiconductor layers are made of single crystal semiconductor material.

7. A process for forming an ultra dense dynamic random access memory array comprising the steps of

providing a first semiconductor substrate (21) of a first conductivity type having a region (22) of second conductivity type extending from the surface of said first substrate partially into said first substrate (21), said first substrate (21) being disposed over a second substrate (8) of first conductivity type and spaced from said first substrate (21) by a layer (20) of insulation,

forming a first plurality of insulation filled trenches (17) (25) which extend from said surface into said second substrate (8) leaving a plurality of spaced apart upstanding regions consisting of portions of said first (21) and second substrates (8) and said insulation layer (20),

forming a second plurality of trenches (32) in said plurality of upstanding regions which extend from said surface into said second substrate (8) leaving a plurality of device regions (4) (5) and simultaneously forming a third plurality of trenches in said insulation filled trenches (17) (25) each of said third plurality of trenches being disposed between a pair of trenches (32) of said second plurality of trenches (32) and extending partially into said insulation filled trench (17) (25) to a given depth,

refilling said second (32) and third plurality of trenches with conductive material (11,12),

forming a fourth plurality of trenches in selected of said second plurality of trenches (32) filled with conductive material (11) to a depth greater than said given depth,

forming insulation (10) at the bottom of each of said fourth plurality of trenches to a thickness sufficient to raise the level of each of said fourth plurality of trenches to said given depth providing with the bottoms of said third plurality of trenches a plurality of insulating gate conductor channels extending orthogonally with respect to said insulation filled trenches (17) (25).

8. A process according to claim 7 further including the steps forming a pair of gate conductors (6) in each of said channels in insulated spaced relationship with adjacent device regions (4),

depositing insulating material (15) in each of said channels to electrically isolate the gate conductors (6) in each channel from each other,

introducing a first conductivity type dopant region (3) into said region of second conductivity type (4) in each of said device regions (4) (5),

planarizing said insulating material (15), and

forming a plurality of conductors (16) disposed in orthogonal relationship with said gate conductors (6) each of said conductors (16) contacting a plurality of said first conductivity type dopant regions (3).

9. A process according to claim 7 wherein said semiconductor substrates are made of single crystal semiconductor material.

10. A process according to claim 7 wherein said layer of insulation is silicon dioxide.

11. A process according to claim 7 wherein said insulation filled trenches are filled with silicon dioxide.

12. A process according to claim 7 wherein the step of forming a first plurality of insulation filled trenches includes the steps of:

masking the surface of said first semiconductor substrate to expose portions of said surface,

etching said substrate to form said plurality of trenches and

chemically vapor depositing said insulation into said first plurality of insulation filled trenches.

13. A process according to claim 7 wherein the step of forming a second plurality of trenches and simultaneously forming a third plurality of trenches includes the steps of:

forming layers of a nitride, oxide and a nitride in that order on said surface and over said insulation filled trenches,

patterning said last mentioned nitride layer leaving spaced apart nitride masking regions,

depositing a layer of polycrystalline semiconductor conformally over said spaced apart nitride regions and reactively ion etching said polycrystalline semiconductor to form sidewall spacers on the sides of each of said spaced apart nitride masking regions,

removing said spaced apart masking regions,

patterning said first mentioned nitride layer and said oxide layer to expose surface portions of said substrate and said insulation filled trenches, and,

reactively ion etching said exposed surface portion of said substrate and said insulation filled trenches to form said second and third plurality of trenches simultaneously.

14. A process according to claim 7 wherein the step of refilling said trenches with conductive material includes the steps of:

forming a composite oxide-nitride layer and a protective layer of polycrystalline semiconductor in said second plurality of trenches,

subjecting said second plurality of trenches to reactive ion etching to remove said protective layer of polycrystalline layer from said second plurality of trenches and said composite oxide-nitride layer from the bottoms of said second plurality of trenches,

depositing polycrystalline semiconductor material in said second and third plurality of trenches and,

polishing said semiconductor material to planarize the surface of said memory array.

15. A process according to claim 7 wherein the step of forming a fourth plurality of trenches is selected of said second plurality of trenches filled with conductive material includes the steps of:

reactively ion etching said selected of said second plurality of trenches to form said fourth plurality of trenches in said conductive material.

16. A process according to claim 7 wherein the step of forming insulation at the bottom of each of said fourth plurality of trenches includes the step of oxidizing the topmost portion of said conductive material.