Process for fabricating a high-speed CMOS TTL semiconductor device

• US 4,920,066 A
• Filed: 12/30/1988
• Issued: 04/24/1990
• Est. Priority Date: 12/31/1987
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sang-Suk, Hong, Pil-Young, Oh, Tae-Yup, Kim, Chun-Joong
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/292,106
• Time in Patent Office: 480 Days
• Field of Search: 437/56, 437/57, 437/195, 357/23.11, 357/42
• US Class Current: 438/227
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0927 comprising a P-well only in the substrate

Abstract

A process for fabricating a high-speed CMOS TTL semiconductor device, wherein the operational speed of a semiconductor device is controlled by adjusting the capacitance of its field region. The capacitance of the field region is adjusted by the thickness thereof, which is determined by the control of diffusion heating cycles in the fabrication sequence according to the invention.

Claims

1. A process for fabricating a semiconductor device, comprising the steps of:

forming a second conductivity type well region over a first conductivity type silicon semiconductor substrate;

forming successively a first oxide layer and a nitride layer over said substrate;

selectively removing portions of said nitride layer over a first MOS transistor region on said well region, a second transistor region on said substrate, and channel-stop regions around said second transistor region;

forming a field oxide layer in the first MOS transistor, second transistor and channel-stop regions exposed by said step of selectively removing portions of said nitride layer,

forming drain and source of said first MOS transistor over said well region, and stop-channel regions in said substrate;

forming ohmic contact regions in an edge of said well region, and drain and source of said second MOS transistor between said stop-channel regions over said substrate;

forming a second oxide layer on the whole surface of said substrate to form a gate oxide layer after removing said nitride layer and said first oxide layer of the gate regions of said first and second MOS transistors;

forming contact windows for contacting the source and drain of said first and second MOS transistors;

forming a pattern of a first metal layer to form electrodes of said first and second MOS transistors;

forming a pattern of low temperature oxide layer over said first metal layer to insulate a specified portion;

forming a pattern of a second metal layer connected with first metal layer through said contact windows, being insulated from said first metal layer by said low temperature oxide layer; and

forming a protection layer over said second metal layer.

2. A process as claimed in claim 1, further comprising the steps for concurrently removing the nitride layers over the edge region of said second conductivity type well region, a region to form said first MOS transistor on said well region, a region to form said second transistor on said substrate, and the stop-channel region to be formed around said second MOS transistor region, after said step of forming successively the first oxide layer and the nitride layer over said substrate, and then forming said field oxide layer in the regions exposed by removing the nitride layers said nitride layer by a heat treatment process.

3. A process as claimed in claim 2, further comprised of forming said second conductivity type well by implanting second conductivity type ions in a dose of 2×

10¹⁵ -3×

10¹⁵ ions/cm² with an energy of 40-50 KeV, and thereon heat-treating for the junction depth to reach 5-6 μ

m.

4. A process as claimed in claim 2, wherein the drain and source of said first MOS transistor, and said stop-channel region are formed by ion-implanting phosphorus and arsenic ions, and thereupon heat-treating for a predetermined junction depth.

5. A process as claimed in claim 2, wherein the drain and source of said second MOS transistor, and said ohmic contact region of said well edge are formed by implanting first conductivity N-type ions, and heat-treating for the junction depth to be deeper of the drain and source of said first MOS transistor.

6. A process for fabricating a semiconductor device, comprising the steps of:

forming a second conductivity type well region over a first conductivity type silicon semiconductor substrate;

forming successively a first oxide layer and a nitride layer over said substrate;

selectively removing portions of said nitride layer over a first MOS transistor region on said well region, a second transistor region on said substrate, and channel-stop regions around said second transistor region;

forming a field oxide layer in the first MOS transistor, second transistor and channel-stop regions exposed by said step of selectively removing portions of said nitride layer,

forming a drain and a source of a first MOS transistor over said well region, and stop-channel regions in said substrate;

forming ohmic contact regions in an edge of said well region, and drain and a source of second MOS transistor between said stop-channel regions over said substrate;

forming a second oxide layer on the surface of said substrate to form a gate oxide layer after removing said nitride layer and said first oxide layer of the gate regions of said first and second MOS transistors;

forming contact windows to the source and drain of said first and second MOS transistors;

forming a pattern of a first metal layer to form electrodes of said first and second MOS transistors; and

forming a pattern of low temperature oxide layer over said first metal layer.

7. A process as claimed in claim 6, further comprising the steps for concurrently removing the nitride layer over the edge region of said second conductivity type well region, a region to form said first MOS transistor on said well region, a region to form said second transistor on said substrate, and the stop-channel region to be formed around said second MOS transistor region, after said step of forming successively the first oxide and the nitride layer over said substrate, and then forming said field oxide layer layer in the regions exposed by removing the nitride layers said nitride layer.

8. A process as claimed in claim 7, further comprised of forming said second conductivity type well by implanting second conductivity type ions in a dose of 2×

10¹⁵ -3×

10¹⁵ ions/cm² with an energy of 40-50 KeV, and thereon heat-treating for the junction depth to reach 5-6 μ

m.

9. A process as claimed in claim 7, wherein the drain and source of said first MOS transistor, and said stop-channel region are formed by ion-implanting phosphorus and arsenic ions, which is thereupon heat-treating for a predetermined junction depth.

10. A process as claimed in claim 7, wherein the drain and source of said second MOS transistor, and said ohmic contact region of said well edge are formed by implanting first conductivity N-type ions, and heat-treating for the junction depth to be more than that of the drain and source of said first MOS transistor.