Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof

• US 4,920,074 A
• Filed: 02/25/1988
• Issued: 04/24/1990
• Est. Priority Date: 02/25/1987
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimizu, Ichio, Nakamura, Soichiro, Hoshi, Akio, Okada, Sumio
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Soltz, David
• Application Number:
  US07/160,177
• Time in Patent Office: 789 Days
• Field of Search: 357/70, 357/72, 357/74, 437/217, 437/219, 437/220, 437/211, 29/856, 361/421
• US Class Current: 29/827
• CPC Class Codes: H01L 21/4821 Flat leads, e.g. lead frames with or without insulating supports
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48799 Principal constituent of the connecting portion of the wire connector being Copper (Cu)
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 Capillary
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85181 connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01205 : 5N purity grades, i.e. 99.999%
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/10689 : Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2201/1084 : Notched leads
• CPC Class Codes: H05K 2201/10924 : Leads formed from a punched metal foil affixing a prefabricated self-supporting metal foil pattern H05K3/202
• CPC Class Codes: H05K 3/3426 : characterised by the leads
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49172 : by molding of insulating material

Abstract

The present invention provides a surface mount Gull-Wing type resin-encapsulating package for encapsulating a semiconductor chip, wherein the cut face (outer tip end) of each outer lead is formed to have a smaller cross-sectional area than that of each outer lead, for improving the extension of solder to the cut face of that lead. Such relatively smaller cross-sectional area of the outer tip end of each outer lead reduces the exposed area of the lead material when disconnecting the leads from the frame in separating the device from the frame.

Claims

1. A process for manufacturing a surface mount resin-encapsulated semiconductor device using a lead frame formed from a metal film into a predetermined shape, wherein the process comprises the steps of:

(a) forming a plurality of resin encapsulating bodies, each having paired main upper and lower surfaces, each resin encapsulating body encapsulating a corresponding semiconductor device, the plurality of resin encapsulating bodies being formed at a plurality of predetermined locations of a lead frame comprising a frame member and leads, each of the leads having a lead part, including a free end, protruding out from a resin encapsulating body, the frame member and leads being connected via connecting portions extending between the frame member and leads, each of the leads and the connecting portions having a cross-sectional area, the cross-sectional area of the connecting portions being smaller than the cross-sectional area of the leads;

(b) forming a soldering layer on the surface of said lead frame subsequent to forming the plurality of resin encapsulating bodies;

(c) disconnecting each lead and the frame member at the connecting portions between said frame member and each of the leads, subsequent to the step of forming the soldering layer; and

(d) shaping the free end, and the vicinity thereof, of each of the leads into such a shape that the free end and vicinity thereof is situated at a position below the main lower surface of the resin encapsulating body from which the respective lead protrudes, substantially in parallel with the main surface of the resin encapsulating body and extending away from said encapsulating body.

2. A process for manufacturing the semiconductor device as defined in claim 1, wherein the resin encapsulating bodies are formed by a transfer molding process.

3. A process for manufacturing the semiconductor device as defined in claim 1, wherein the step of forming a soldering layer forms the soldering layer on exposed surfaces of the parts of the leads protruding out from the respective resin encapsulating body, and on exposed surfaces of the connecting portions.

8. A process for manufacturing the semiconductor device as defined in claim 1, wherein the cross-sectional area of the connecting portions is smaller than the cross-sectional area of the leads at a location of each of the connecting portions where each lead and the frame member are disconnected, the disconnecting step disconnecting each lead and the frame member at said location.

10. A process for manufacturing the semiconductor device as defined in claim 1, wherein the step (c) is conducted prior to the step (d).

11. A process for manufacturing the semiconductor device as defined in claim 1, wherein the ratio of cross-sectional area of the connecting portions to that of the lead is from 1/5 to 2/3.

12. A process for manufacturing the semiconductor device as defined in claim 1, wherein the connecting portions are provided with a smaller cross-sectional area than the cross-sectional area of the outer leads by providing recesses at at least one side of the connecting portions so as to reduce the cross-sectional area of the connecting portions as compared to the cross-sectional area of the connecting portions without the recesses.

13. A process for manufacturing the semiconductor device as defined in claim 1, wherein the connecting portions are provided with a smaller cross-sectional area than that of the leads by providing the connecting portions with a reduced thickness as compared to the thickness of the leads.

14. A process for manufacturing the semiconductor device as defined in claim 1, wherein the connecting portions are provided with a smaller cross-sectional area than that of the outer leads by providing recesses at the connecting portions so as to reduce the cross-sectional area of the connecting portions as compared to the cross-sectional area of the connecting portions without the recesses.

4. A method of surface mounting a resin-encapsulated semiconductor device, comprising the steps of:

(a) forming a solder-containing composition layer of a predetermined pattern over land pads of a printed wiring substrate having a plurality of such land pads at least on one main surface thereof;

(b) placing a plurality of resin-encapsulated semiconductor devices onto said composition layer, the resin-encapsulated semiconductor devices having leads protruding out from the resin encapsulation and extending to free ends thereof, the free ends terminating with a front face, the plurality of resin-encapsulated semiconductor devices being placed such that the free ends of the leads are substantially in parallel with the main surface on which the solder-containing composition layer has been formed;

in which

each of the free ends of the leads is tapered toward the front face and is coated with a soldering layer except for the front face, the front face being exposed;

(c) heating the leads and the composition layer substantially simultaneously, thereby melting the solder; and

(d) cooling the solder, thereby completing the soldering.

5. A method of surface mounting as defined in claim 4, wherein the melting of the solder in the step (c) is carried out by a vapor phase reflow method.

6. A method of surface mounting as defined in claim 5, wherein the composition layer comprises a solder paste.

7. A method of surface mounting as defined in claim 6, wherein the main surface on which the solder-containing composition has been formed, except for the land pads, is coated with solder-resist.

9. A method of surface mounting as defined in claim 4, wherein a remaining portion of each of the leads, other than the free ends, have a cross-sectional area, the cross-sectional area of the remaining portion of each of the leads being greater than the area of the front face of each free end.

15. A method of surface mounting as defined in claim 4, wherein, upon melting the solder, the solder flows so as to cover the exposed front face of the free ends of the leads.