Conductance-modulated integrated transistor structure
First Claim
1. An integrated CMOS transistor structure comprising a semiconductor body having a major surface with a first device region of a first conductivity type and a second device region of a second conductivity type therein,a first device formed in said first device region and including a source region and a drain region of said second conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and drain regions forming a p-n junction with said first device region, a gate contact between said source and drain regions and insulatively spaced from said device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on.a second device formed in said second device region and including a source region and a drain region of first conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and said drain regions forming a p-n junction with said second device region, a gate contact between said source and drain regions and insulatively spaced from said second device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on.input connector means interconnecting said gate contacts of said first and second devices, andoutput connector means interconnecting said Schottky contacts of said first and second devices.
0 Assignments
0 Petitions
Accused Products
Abstract
Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.
-
Citations
6 Claims
-
1. An integrated CMOS transistor structure comprising a semiconductor body having a major surface with a first device region of a first conductivity type and a second device region of a second conductivity type therein,
a first device formed in said first device region and including a source region and a drain region of said second conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and drain regions forming a p-n junction with said first device region, a gate contact between said source and drain regions and insulatively spaced from said device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on. a second device formed in said second device region and including a source region and a drain region of first conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and said drain regions forming a p-n junction with said second device region, a gate contact between said source and drain regions and insulatively spaced from said second device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on. input connector means interconnecting said gate contacts of said first and second devices, and output connector means interconnecting said Schottky contacts of said first and second devices.
Specification