Conductance-modulated integrated transistor structure

• US 4,920,399 A
• Filed: 10/10/1989
• Issued: 04/24/1990
• Est. Priority Date: 09/12/1988
• Status: Expired due to Fees

• Current Assignee: Linear Integrated Systems, Inc.
• Original Assignee: Linear Integrated Systems, Inc.
• Inventors: Hall, John H.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): PRENTY, MARK V
• Application Number:
  US07/418,962
• Time in Patent Office: 196 Days
• Field of Search: 357/42, 357/15, 357/43, 357/46, 357/23.7
• US Class Current: 257/351
• CPC Class Codes: H01L 27/0711 in combination with bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0927 comprising a P-well only in the substrate

Abstract

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Claims

1. An integrated CMOS transistor structure comprising a semiconductor body having a major surface with a first device region of a first conductivity type and a second device region of a second conductivity type therein,

a first device formed in said first device region and including a source region and a drain region of said second conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and drain regions forming a p-n junction with said first device region, a gate contact between said source and drain regions and insulatively spaced from said device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on.

a second device formed in said second device region and including a source region and a drain region of first conductivity type, said source and drain regions being spaced apart by a channel region and each of said source and said drain regions forming a p-n junction with said second device region, a gate contact between said source and drain regions and insulatively spaced from said second device region, an ohmic contact solely to said source region and a Schottky contact solely to said drain region, said Schottky contact forming a Schottky diode with said drain region which is forward biased and injecting minority carriers into said channel region when said gate contact is voltage biased on.

input connector means interconnecting said gate contacts of said first and second devices, and

output connector means interconnecting said Schottky contacts of said first and second devices.

2. The integrated transistor structure as defined by claim 1 wherein said semiconductor body comprises a semiconductor substrate and an epitaxial layer formed on a surface of said substrate.

3. The integrated transistor structure as defined by claim 2 wherein said first device further includes a first buried layer of said first conductivity type, and said second device further includes a second buried layer of said second conductivity type, wherein said and second buried layers collect some of the minority carriers injected from said Schottky diodes.

4. The integrated transistor structure as defined by claim 3 wherein the dopant concentration in said drain regions is sufficiently low to prevent said Schottky contacts from forming ohmic contacts with said drain regions.

5. The integrated transistor structure as defined by claim 1 and further including a supporting substrate having an insulating surface and wherein said semiconductor body is formed on said insulated surface and said first and second device regions comprise semiconductor layers on said insulated surface.

6. The integrated transistor structure as defined by claim 5 wherein the dopant concentration of said drain regions is sufficiently low to prevent said Schottky contacts from forming ohmic contacts with said drain regions.