Semiconductor integrated circuit with nonvolatile memory

• US 4,920,518 A
• Filed: 03/28/1989
• Issued: 04/24/1990
• Est. Priority Date: 04/23/1985
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Hideo, Sawase, Terumi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/329,515
• Time in Patent Office: 392 Days
• Field of Search: 365/228, 365/189.01, 371/10, 371/13, 371/21
• US Class Current: 365/228
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A semiconductor integrated circuit with a non-volatile memory has a plurality of nonvolatile data memory elements arranged in a matrix and a means for reading data from the memory elements in accordance with an address signal which specifies a position in the matrix. A protecting data memory element for storing at least one-bit protection data is disposed in the matrix. Whether operations such as programming (i.e., writing), erasing or reading with respect to the data memory elements will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element. In other words, data security in an arbitrary area of the matrix can be accomplished based on the content of the protecting data memory element.

Claims

1. A microcomputer comprising:

a nonvolatile semiconductor memory, and

a processing unit,

said nonvolatile semiconductor memory comprising;

a plurality of data memory elements arranged in a matrix;

a first means for accessing a selected one element within said plurality of data memory elements in accordance with an address signal specified with respect to said matrix;

a protecting data memory element for storing at least 1-bit protection data disposed within said matrix; and

a second means for reading out the content of said protecting data memory element, whereby whether a programming, erasing or reading operation with respect to said selected one element is to be allowed or inhibited is determined in accordance with the content of said protecting data memory element, said content being read by said second means, wherein said data memory elements are respectively comprised of an electrically erasable and programmable memory element.

2. A microcomputer according to claim 1, wherein said nonvolatile semiconductor memory further comprises a latch for storing said content read out from said protecting data memory element, said latch outputting a programming inhibiting signal and/or an erasing inhibiting signal with respect to said selected one element.

3. A microcomputer comprising:

a nonvolatile semiconductor memory, and

a processing unit,

said nonvolatile semiconductor memory comprising;

a plurality of data memory elements arranged in a matrix;

a first means for accessing a selected one element within said plurality of data memory elements in accordance with an address signal specified with respect to said matrix;

a protecting data memory element for storing at least 1-bit protection data disposed within said matrix; and

a second means for reading out the content of said protecting data memory element, whereby whether a programming, erasing or reading operation with respect to a group of said data memory elements arrayed in a line in the row direction of said matrix is to be allowed or inhibited is determined in accordance with the content of said protecting data memory element, said content being read by said second means, wherein said data memory elements are respectively comprised of an electrically erasable and programmable memory element.

4. A microcomputer comprising:

a semiconductor integrated circuit including a plurality of electrically erasable and programmable nonvolatile semiconductor memory elements arranged in a matrix and further including a circuit unit for programming/erasing at least a selected one of said elements within a variable time duration, and

a processing unit,

wherein said circuit unit comprises;

a timer means operating synchronously with an external clock; and

a register means for setting data corresponding to said variable time duration, wherein said timer means generates a control signal for programming/erasing said selected one element within a predetermined time duration in response to a start signal for the programming/erasing operation, said data set in said register means and said external clock, whereby the predetermined time duration is made variable in accordance with data set in said register means.

5. A microcomputer according to claim 4, wherein a data processing unit is arranged in the same semiconductor substrate as that for said semiconductor integrated circuit, said data processing unit and said integrated circuit using a common clock signal.

6. A microcomputer comprising:

a semiconductor integrated circuit; and

a processing unit,

wherein the semiconductor integrated circuit comprises;

a plurality of electrically erasable and programmable nonvolatile semiconductor memory elements arranged in a matrix;

a first means for accessing a selected one element within said plurality of memory elements in accordance with an address signal specified with respect to said matrix, said address signal being generated from a processing unit;

a second means for transmitting data between said plurality of memory elements and said processing unit, said second means temporarily latching said data;

a third means for latching said address signal from said processing unit;

a fourth means for controlling said second and third means in response to control signals from said processing unit; and

a fifth means for delaying a programming/erasing control signal of said control signals for a period of time during which reading of data from said selected one element within said nonvolatile memory elements can be accomplished, wherein said processing unit gives a first instruction to read a present command from said nonvolatile memory elements, a second instruction to read an operand from said nonvolatile memory elements, a third instruction to write a result of a calculation of said operand into said nonvolatile memory elements and a fourth instruction to read a subsequent command from said nonvolatile memory elements, and wherein said semiconductor integrated circuit executes said instructions in the order of said first instruction, said second instruction, then said fourth instruction and thereafter said third instruction.

7. A microcomputer according to claim 6, wherein said fifth means is arranged in a semiconductor substrate of said semiconductor integrated circuit together with said nonvolatile memory elements as well as said processing unit.