Memory error correction system

• US 4,920,539 A
• Filed: 06/20/1988
• Issued: 04/24/1990
• Est. Priority Date: 06/20/1988
• Status: Expired due to Fees

• Current Assignee: CVSI, Inc. (NCR Voyix Corporation)
• Original Assignee: Prime Computer, Inc. (DR Holdings, Inc. of Delaware)
• Inventors: Albonesi, David
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US07/209,285
• Time in Patent Office: 673 Days
• Field of Search: 371/38, 371/37, 371/21, 371/5, 371/13, 371/16.5, 371/40.1, 371/40.2, 371/40.3, 371/40.4, 371/29.1, 371/5.1, 371/21.1, 371/21.2, 365/200, 364/200, 364/900
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.

Claims

1. In a computer system having a processing unit, memory, memory control unit, system communication bus, and bus control unit, a method of correcting memory errors, comprising the steps of, detecting a data error while data is being transferred from memory to the system bus and generating corresponding corrected data if a data error is detected, storing at the memory control unit at least the address field and source identification code associated with the just detected data error, generating a bus request signal coupled to the bus control unit, said bus control unit, in turn, generating a bus grant signal, said memory control unit in response to said bus grant signal issuing a read message on the system bus having an address field and destination identification code corresponding to said stored address field and source identification code, and in response to said read message, the device indicated by said identification code, writing back to memory the correct data corresponding to said address field.

2. A method as set forth claim 1 wherein said bus grant signal is generated on a prioritized basis.

3. A method as set forth in claim 1 wherein the step of detecting a data error and generating corresponding corrected data includes generating an error correcting code when data is written to memory and checking the data read from memory for an error.

4. A method as set forth in claim 3 further including correcting the data read from memory.

5. A method as set forth in claim 4 wherein the detected error is a soft memory failure.

6. A method as set forth in claim 5 wherein the error is a correctable error adapted to be corrected before it becomes uncorrectable.

7. A method as set forth in claim 1 wherein the step of writing back to memory to correct the data includes providing a writeback cache responsive to a read request.

8. A method as set forth in claim 1 further including correcting the data read from memory.

9. A method as set forth in claim 1 wherein the detected error is a soft memory failure.

10. A method as set forth in claim 1 wherein the error is a correctable error adapted to be corrected before it becomes uncorrectable.

11. A memory error correction system for use in a computer apparatus having a plurality of processors, a system bus operatively connected to the plurality of processors, a memory susceptible to having soft memory failures, and memory controller means operatively connected to the memory, said system comprising, means for detecting a data error while data is being transferred from memory to the system bus and for correcting that transferred data if a data error is detected, means for storing at least the address field and source identification code associated with the just detected data error, means responsive to data error detection for generating a generic bus request signal, means responsive to said bus request signal for providing a bus grant signal, means responsive to the bus grant signal for issuing a read message on the system bus having an address field and destination identification code corresponding to said stored address field and source identification code, and means responsive to said read message for writing back to memory the correct data corresponding to said address field.

12. A system as set forth in claim 11 wherein said means for detecting a data error and for correcting that data includes error check logic.

13. A system as set forth in claim 12 wherein said means for storing includes data storage register means and command buffer means.

14. A system as set forth in claim 13 wherein the means responsive to data error detection for generating a generic bus request includes a fetch sequencer responsive to the data error and a request/grant logic means.

15. A system as set forth in claim 14 including a bus control unit having arbitration logic means intercoupled with said request/grant logic means to provide the bus grant signal on a prioritized basis.

16. A system as defined in claim 15 wherein said fetch sequence initiates said read message and further including OPCODE select means.

17. A system as defined in claim 16 wherein said means for issuing a read message includes transceiver means, said fetch sequencer selecting the command buffer address and source ID fields to be the destination ID and address fields of the pending read message.

18. A system as defined in claim 11 wherein each processor includes a writeback memory defining the means for writing back to memory.

19. A system as defined in claim 18 wherein each writeback memory comprises a writeback cache.

20. A system as defined in claim 11 wherein said means for detecting a data error and for correcting that transferred data comprises error correcting code check and correct logic.

21. In a computer system having a processing unit, memory, memory control unit, a system communication bus, and bus control unit, a method of correcting memory errors, comprising the steps of, detecting a data error while data is being transferred from memory to the system bus and generating corresponding corrected data if a data error is detected, storing at the memory control unit at least the address field associated with the just detected data error, generating a bus request signal coupled to the bus control unit, said bus control unit, in turn, generating a bus grant signal, said memory control unit in response to said bus grant signal issuing a read message on the system bus having an address field corresponding to said stored address field, and in response to said read message, writing back to memory the correct data corresponding to said address field.

22. A method as set forth in claim 21 wherein said bus grant signal is generated on a prioritized basis.

23. A method as set forth in claim 21 wherein the step of detecting a data error includes generating an error correcting code when data is written to memory and checking the data read from memory for an error.

24. A method as set forth in claim 23 further including correcting the data read from memory.

25. A method as set forth in claim 24 wherein the detected error is a soft memory failure.

26. A method as set forth in claim 25 wherein the error is a correctable error adapted to be corrected before it becomes uncorrectable.

27. A method as set forth in claim 21 wherein the step of writing back to memory to correct the data includes providing a writeback cache responsive to a read request.

28. A method as set forth in claim 21 further including correcting the data read from memory.

29. A method as set forth in claim 21 wherein the detected error is a soft memory failure.

30. A method as set forth in claim 21 wherein the error is a correctable error adapted to be corrected before it becomes uncorrectable.

31. A memory error correction system for use in a computer apparatus having a plurality of processors, a system bus operatively connected to the plurality of processors, a memory susceptible to having soft memory failures, and memory controller means operatively connected to the memory, said system comprising, means for detecting a data error while data is being transferred from memory to the system bus and for correcting that data if a data error is detected, means for storing at least the address field associated with the just detected data error, means responsive to the data error detection for generating a generic bus request signal, means responsive to said bus request signal for providing a bus grant signal, means responsive to the bus grant signal for issuing a read message on the system bus having an address field corresponding to said stored address field, and means responsive to said read message for writing back to memory the correct data corresponding to said address field.

32. A system as set forth in claim 31 wherein said means for detecting a data error and for correcting that transferred data includes error check logic.

33. A system as set forth in claim 32 wherein said means for storing includes data storage register means and command buffer means.

34. A system as set forth in claim 33 wherein the means responsive to data error detection for generating a generic bus request includes a fetch sequencer responsive to the data error and a request/grant logic means.

35. A system as set forth in claim 34 including a bus control unit having arbitration logic means intercoupled with said request/grant logic means to provide the bus grant signal on a prioritized basis.

36. A system as defined in claim 35 wherein said fetch sequence initiates said read message and further including OPCODE select means.

37. A system as defined in claim 36 wherein said means for issuing a read message includes transceiver means, said fetch sequencer selecting the command buffer address field to be the destination address field of the pending read message.

38. A system as defined in claim 31 wherein each processor includes a writeback memory defining the means for writing back to memory.

39. A system as defined in claim 38 wherein each writeback memory comprises a writeback cache.

40. A system as defined in claim 31 wherein said means for detecting a data error and for correcting that transferred data comprises error correcting code check and correct logic.

41. A method of correcting memory errors, comprising the steps of, detecting a data error while data is being transferred from memory and generating corresponding corrected data if a data error is detected, storing at least the address field and source identification code associated with the just detected data error, generating a bus request signal, generating a bus grant signal in response to the bus request signal, issuing a read message in response to the bus grant signal on the system bus having an address field and destination identification code corresponding to said stored address field and source identification code, and in response to said read message, a device indicated by said identification code, writing in the memory the correct data corresponding to said address field.

42. A method of correcting memory errors, comprising the steps of, detecting a data error in data stored in memory and generating corresponding corrected data if a data error is detected, storing at least the address field associated with the just detected data error, generating a bus request signal, generating a bus grant signal in response to the bus request signal, issuing a read message in response to the bus grant signal on the system bus having an address field corresponding to said stored address field, and in response to said read message, writing in the memory the correct data corresponding to said address field.