Supply circuit for a hall sensor multiplication circuit

• US 4,922,123 A
• Filed: 03/16/1989
• Issued: 05/01/1990
• Est. Priority Date: 03/18/1988
• Status: Expired due to Fees

• Current Assignee: Iskra Stevci - Industrija Merilne In Upravljalne Tehnike Kranj
• Original Assignee: Iskra-Sozd Elektrokovinske Industrije N.Sol.O.
• Inventors: Rozman, Miro
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): CUNNINGHAM, TERRY D
• Application Number:
  US07/324,414
• Time in Patent Office: 411 Days
• Field of Search: 307/309, 324/117 H, 324/117 R, 324/127, 324/142, 338/32 R, 338/32 H, 323/211, 323/322, 323/349
• US Class Current: 327/356
• CPC Class Codes: G01R 21/08 by using galvanomagnetic-effect devices, e.g. Hall-effect devices
• CPC Class Codes: G06G 7/162 using galvano- magnetic effects, e.g. Hall effect; using similar magnetic effects

Abstract

Supply circuit SC for a Hall sensor multiplication circuit HSC makes it possible to produce both circuits in monolithic technology on a common substrate and yet accomplish the polarity reversal of the output voltage U_H of the multiplication circuit HSC with such accuracy that at said reversal the absolute value of the voltage U_H is preserved with an accuracy of 0.01%.

Claims

1. Supply circuit for a Hall sensor multiplication circuit, characterized in

that a load terminal (L1) is through a resistor (R3) connected, through a switch (23) to the first terminal of an adjustable resistor (Rk), and through a switch (24) to the output terminal (O) and through a switch (26) to the first terminal of a resistor (R4), whose second terminal is connected to a grounded load terminal (L2), and through a switch (25) to the first terminal of the resistor (Rk),

that the second terminal of the resistor (Rk) is connected to a common terminal of switches (15,16), whose second terminal is connected to the common terminal of switches (11,13;

12,14, resp.) and to the first terminal of resistors (R1,R2, resp.) the second terminal of these resistors being connected to the output of an operational amplifier (A_I), whose inverting input is connected to the second terminal of the switches (11,12) and whose noninverting input is connected to the second terminal of the switches (13,14),

that the output terminal (O) is connected through switches (17,18) to the first terminal of the resistors (R1,R2, resp.),

that the signal input terminal (SI) is connected to the control terminal of the switches (23,26), and through inverters (27,28) to the control terminal of the switches (24,25, resp.) and to the input of a frequency divider (29),

and that the output of the frequency divider (29) is connected to the control terminal of the switches (11,14,15,18) and through inverters (19,20,21,22) to the control terminal of the switches (13,12,17,16, resp.).

2. Circuit as recited in claim 1, characterized in that the resistances of the resistors (R1,R2) are equal and the resistance of the adjustable resistor (Rk) equals twice the resistance of the load at the circuit output (O).