Phase-locked loop delay line

• US 4,922,141 A
• Filed: 06/03/1988
• Issued: 05/01/1990
• Est. Priority Date: 10/07/1986
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Lofgren, Karl M. J., Ouyang, Kenneth W., Shearer, Gerald W.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/205,517
• Time in Patent Office: 697 Days
• Field of Search: 307/590, 307/591, 307/594, 307/595, 307/597, 307/602, 307/603, 307/605, 307/606, 307/511, 307/525, 307/358, 307/359, 328/155, 328/55, 328/66
• US Class Current: 327/158
• CPC Class Codes: H03H 9/38 with adjustable delay time H03H9/40, H03H9/42 take precedence
• CPC Class Codes: H03K 2005/00104 using a reference signal, e.g. a reference clock
• CPC Class Codes: H03K 2005/0013 Avoiding variations of delay due to power supply
• CPC Class Codes: H03K 2005/00195 using FET's
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.

Claims

1. A circuit for providing a signal having a precise delay with respect to a digital input signal, comprising:

a single reference frequency source for generating a periodic input signal of constant period;

a variable delay circuit for receiving the input signal and generating an output signal which is delayed with respect to the input signal, herein the delay circuit includes a control voltage input to control the amount of delay;

control means for comparing the phase between the input signal and the output signal and varying the amount of delay provided by the delay circuit to achieve and maintain a desired delay equal to an integer multiple of said constant period, wherein the control means includes;

means for generating the control voltage as a function of the phase difference between the input signal and output signal, and

means, coupled to the means for generating, for determining whether the phase of the input signal leads or lags the phase of the output signal,

wherein the means for generating the control voltage includes a charge pump having a capacitor which is charged or discharged, wherein the voltage across the capacitor is the control voltage, and

wherein the means for determining generates a first signal causing the charge pump to charge the capacitor in a first direction when the phase of the input signal leads the phase of the output signal and generates a second signal causing the charge pump to charge the capacitor in the opposite direction when the phase of the input signal lags the phase of the output signal.

2. A circuit as in claim 1 wherein the means for determining includes a phase detector which receives the input signal and output signal and generates the first signal during a time period between a rising edge of the input signal and the next rising edge of the output signal and generates the second signal during a time period between a rising edge of the output signal and the next rising edge of the input signal.

3. A circuit as in claim 2 wherein the phase detector includes a first D-type flip-flop which is set by a rising edge of the input signal and a second D-type flip-flop which is set by a rising edge of the output signal, a first logic gate operatively coupled to receive an output from each flip-flop and provide said first signal and a second logic gate operatively coupled to receive an output from each flip-flop and provide said second signal.

4. A circuit as in claim 1 wherein the delay circuit includes a plurality of delay stages, each delay stage generating a delay stage output signal and wherein said control means includes harmonic control means coupled to said delay stages so as to receive said delay stage output signals for causing the delay stage output to be delayed with respect to the input signal by a predetermined number of periods of the input signal.

5. A circuit as in claim 4 wherein the predetermined number of period is one and wherein the harmonic control means includes means for monitoring the output signal to determine whether it has a desired timing relationship to the input signal and means coupled to the means for monitoring, for correcting the value of the control voltage to achieve a delay of one period if an improper timing relationship is detected.

6. A circuit as in claim 5 wherein the means for correcting comprises means for resetting the control voltage to a value such that the delay circuit provides an output signal having a minimum delay, whereby the circuit will thereafter operate to increase the delay of the output signal to achieve a delay of one period of the input signal.

7. A circuit as in claim 1 wherein the delay circuit includes a plurality of series connected inverters and means for modulating the switching speed of the inverters.

8. A circuit as in claim 7 wherein each inverter is comprised of a CMOS transistor pair and wherein the means for modulating comprises additional transistors coupled between the inverters and power supply connectors, wherein the control voltage is applied to the additional transistors to modulate the current supplied to the inverters and thereby modulate their switching speed.

9. A phase-locked circuit for providing an output signal having precise delay with respect to a single periodic digital input signal, comprising:

means for providing a single periodic digital input signal of a reference frequency and having a constant period;

variable delay means for receiving the input signal and generating an output signal which is delayed with respect to the input signal by an integer multiple of said constant period;

phase-locked control means for receiving the input signal and the output signal and controlling the variable delay means so that the output signal is locked in phase with respect to the input signal and maintained at a delay of an integer multiple of said constant period, wherein the phase-lock control means includes a phase comparator for comparing the phase of the input signal with the phase of the output signal and generating a first error signal when the phase of the input signal leads the phase of the output signal and a second error signal when the phase of the input signal lags the phase of the output signal; and

correction means coupled to the phase-lock control means and the variable delay means, for generating a control signal in response to the error signals to control the amount of delay of the delay means,

wherein the correction means includes a charge pump having a first capacitor which is charged in a first direction in response to the first error signal and in a second direction in response to the second error signal, wherein the voltage across the capacitor is the control signal for controlling the delay means.

10. The circuit of claim 9 wherein the control means includes means for causing the output signal to be delayed by a predetermined number of periods of the input signal.

11. The circuit of claim 9 wherein the delay means includes a plurality of series connected inverters and means for varying the switching speed of the inverters thereby to vary the delay of the delay means.

12. The circuit of claim 11 further comprising a first power supply connection for receiving externally provided current and wherein each inverter is comprised of a pair of CMOS transistors and wherein the means for varying includes a plurality of first supply transistors coupled between the first power supply connection and the inverters for controlling the application of current to the inverters, wherein the supply transistors are driven by the control signal from the capacitor.

13. The circuit of claim 12 wherein:

the means for varying includes a plurality of second supply transistors coupled between a second power supply connection and the inverters for controlling the application of current to the inverters; and

the correction means includes means, coupled to the second supply transistors, for generating a second control signal to drive the second supply transistors.

14. The circuit of claim 13 wherein the first supply transistors are MOS transistors of first conductivity type and the second supply transistors are MOS transistors of second conductivity type and wherein the means for generating the second control signal controls the value of the second control signal as a function of the value of the first control signal.

15. The circuit of claim 14 wherein the means for generating the second control signal includes:

a current source;

a first control MOS transistor driven by the control signal;

a second control MOS transistor coupled to the current source so as to allow current flow therethrough;

a second capacitor connected to the gate of the second control MOS transistor, wherein the voltage on the second capacitor is the second control signal; and

current control means, coupled to the second control MOS transistor and the first control MOS transistor for driving the second control MOS transistor so that the current through it has a predetermined relationship to the current through the first control MOS transistor.

16. The circuit of claim 15 wherein the current control means includes:

a CMOS inverter having its input connected to its output, wherein the first and second control MOS transistors are connected to supply current to the inverter; and

comparison means, coupled to the output of the CMOS inverter and the gate of the second control MOS transistor, for comparing the output of the inverter to a reference voltage and driving the second control MOS transistor unit the output of the inverter is equal to the reference voltage.

17. The circuit of claim 16 wherein the reference voltage is approximately equal to the switching voltage of the inverter.

18. A circuit for providing a controlled amount of delay to a digital input signal, comprising:

reference frequency means for providing a periodic output signal having a constant period;

a first variable delay circuit for receiving the output of the reference frequency means and providing an output signal having a delay determined by a control signal;

phase lock means for comparing the phase of the output signal of the reference frequency means with the phase of the output signal of the first variable delay circuit and generating the control signal to the first variable delay circuit which causes the output signal of the first variable delay circuit to lock onto the phase of the output of the reference frequency means and be maintained at a delay of an integer multiple of said constant period; and

a second variable delay circuit for receiving a digital input signal and providing an output signal which is delayed with respect to the input signal and maintained at a delay of an integer multiple of said constant period, wherein the control signal is applied to the second variable delay circuit to control the amount of delay and wherein the variation in delay of the first variable delay circuit in response to a change in the control signal is proportional to the change in the amount of delay of the second variable delay circuit in response to the same change in the control signal.

19. A phase-locked loop circuit for provided a signal which is precisely delayed with respect to a single period reference signal of constant period, comprising:

a single reference frequency source for providing the single periodic reference signal of constant period;

a variable delay circuit having a first input for receiving the reference signal and a control input for receiving a control signal, the variable delay circuit providing a periodic output signal which has the same frequency as the reference signal and is delayed with respect to the reference signal by an amount, determined by the control signal, equal to an integer multiple of said constant period;

control means for comparing the phase between the reference signal and the output signal and providing the control signal to the variable delay circuit to vary the amount of delay to achieve a desired phase relationship and maintain said delay at an integer multiple of said constant period, wherein the control means includes;

means, coupled to the control means, for setting the control signal to an initial value which will result in a delay that causes the initial phase error to be in a known direction, a phase detector for comparing the phases of the reference signal and the output signal and generating a first error signal when a phase error of a first direction is detected and a second error signal when a phase error of a second direction is detected, and a charge pump, coupled to the means for setting, for receiving the error signals and generating the control signal in response to the error signals.

20. A circuit as in claim, 19 wherein the phase detector includes:

a first D-type flip-flop clocked by a rising edge of the reference signal;

a second D-type flip-flop clocked by a rising edge of the output signal;

phase comparison control means for enabling the flip-flops in response to a first rising edge of the reference signal whereby the first flip-flop may be clocked by the next rising edge of the reference signal and the second flip-flop may be clocked by the next rising edge of the output signal; and

logic means connected to the outputs of the flip-flops for generating the error signals.

21. A phase-locked loop circuit for providing a signal which is precisely delayed with respect to a periodic reference signal having a constant period, comprising:

a reference frequency source for providing the periodic reference signal of constant period;

a variable delay circuit having a first input for receiving the reference signal and a control input for receiving a control signal, the delay circuit providing a periodic output signal which has the same frequency as the reference signal and is delayed with respect to the reference signal by an amount determined by the control signal equal to an integer multiple of said constant period;

control means, coupled to the reference frequency source and the variable delay circuit, for comparing the phase between the reference signal and the output signal and providing the control signal to the delay circuit to vary the amount of delay to achieve a desired phase relationship and maintain said delay at an integer multiple of said constant period, the control means including means for determining the direction of phase error between the reference signal and output signal and varying the control signal in a direction which will reduce the phase error, wherein the means for determining includes;

a phase detector for comparing the phase of the reference signal and the output signal and generating a first error signal when a phase error of a first direction is detected and a second error signal when a phase error of a second direction is detected; and

a charge pump for receiving the error signals and generating the control signal in response to the error signals, wherein the phase detector includes;

a first D-type flip-flop clocked by a rising edge of the reference signal;

a second D-type flip-flop clocked by a rising edge of the output signal;

phase comparison control means for enabling the flip-flops in response to a first rising edge of the reference signal whereby the first flip-flop may be clocked by the next rising edge of the reference signal and the second flip-flop may be clocked by the next rising edge of the output signal; and

logic means connected to the outputs of the flip-flops for generating the error signals, wherein the phase comparison control means includes a third D-type flip-flop clocked by a rising edge of the reference signal, wherein the output of the third flip-flop controls the enabling of the first and second flip-flops.

22. A circuit as in claim 21 wherein the third flip-flop is configured to provide an output which (a) enables the first and second flip-flops in response to a first rising edge of the reference signal to permit the first flip-flop to be clocked by the next rising edge of the reference signal and (b) resets the first and second flip-flops to a non-enabled condition in response to a third rising edge of the reference signal occurring immediately after said next rising edge of the reference signal.

23. A phase-locked circuit for providing an output signal having precise delay with respect to a period digital input reference signal, comprising:

means for providing a periodic digital input reference signal of a constant reference frequency and period;

first variable delay means for receiving the input reference signal and generating an output reference signal which is delayed with respect to the input reference signal;

phase-lock control means for receiving the input reference signal and the output reference signal and controlling the delay means so that the output signal is locked in phase with respect to the input reference signal and maintained at a delay of an integer multiple of said constant period; and

second variable delay means for receiving an input data signal and generating an output data signal which is delayed with respect to the input data signal, the amount of delay of the second variable delay means being controlled by the phase-lock control means, wherein the change in the delay of the first variable delay means results in a proportional change in the amount of delay of the second variable delay means.

24. A digital delay circuit for delaying one or more digital signals by a precise time delay, comprising:

a reference node for receiving a single periodic reference signal;

master delay means, coupled to the reference node, for receiving the reference signal and delaying the reference signal by an adjustable first time delay having a magnitude and outputting a first delayed signal having a frequency identical to the reference signal and a phase which is delayed relative to the reference signal by said first time delay;

delay detecting means, coupled to the reference node and the master delay means, for detecting the phase relationship between the reference signal and the first delayed signal and for outputting a phase difference signal indicative of the magnitude of the first time delay;

delay control means, coupled to the delay detecting means and the master delay means, for supplying a delay control signal to the master delay means in response to the phase difference signal so as to cause the first time delay indicated by the phase difference signal to converge on a predetermined value and be maintained at said value; and

slave delay means, coupled to the delay control means and having delay characteristics substantially identical to those of the master delay means, for receiving a supplied digital input signal and outputting a second delayed signal having a frequency which is identical to the digital input signal and a phase which is delayed relative to the digital input signal by a second time delay determined in accordance with the delay control signal supplied by the delay control means.

25. A digital delay circuit according to claim 24 wherein the master delay means comprises a plurality of digital delay stages of substantially identical delays, each of the delay stages being controlled by the delay control signal of the delay control means, a first one of the delay stages outputting the first delayed signal and a second one of the delay stages outputting a second delayed signal having a frequency identical to the reference signal and a phase which is delayed relative to the reference signal by a second time delay.

26. A digital delay circuit according to claim 24 wherein the master delay means comprises a plurality of digital delay stages of substantially identical delays, wherein each of the delay stages is controlled by the delay control signal of the delay control means, each of the delay stages comprises a digital logic circuit having a switching speed and a power input for supplying electrical power to the digital logic thereof and each of the delay stages further comprises a current controller, coupled to the digital logic circuit and response to the delay control signal, for controlling the amount of current supplied to the digital logic circuit of the delay stage through its power input and changing the switching speed of the digital logic circuit in response to the delay control signal.

27. A digital delay circuit according to claim 26 wherein the digital logic circuit of each delay stage comprises first and second MOSFET'"'"'s and the current controller comprises a third MOSFET connected in series with the first and second MOSFET'"'"'s.

28. A digital delay circuit according to claim 24 wherein the master and slave delay means are formed on an integrated circuit and include two or more delay stages that are substantially identical.

29. A digital delay circuit according to claim 24 further comprising a single reference signal generator, coupled to the reference node, for supplying the single period reference signal to the reference node.

30. A digital delay circuit according to claim 29 wherein the single reference signal generator includes a crystal oscillator.

31. A digital delay circuit according to claim 24 wherein:

the master delay means includes an input and a first output and a plurality of delay stages each having a tapped delay output for producing samples of the logic state of the reference signal at each of the delay stages; and

the digital delay circuit further comprises harmonic detection means, coupled to the tapped delay outputs, for detecting whether the logic stage of the reference signal at the plurality of delay stages at a particular point in time corresponds to a single cycle of the periodic reference signal being spatially distributed over the master delay means from its input to its first output or whether the waveform corresponds to more than one such cycle.