10 Gigasample/sec two-stage analog storage integrated circuit for transient digitizing and imaging oscillography
First Claim
1. A high speed data acquisition system for storing a succession of sampled values of an analog signal comprising analog signal input means and analog signal output means, a first analog bus connected to said input means and a second analog bus connected to said output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said array for selectively activating each row of said array, column clock means coupled to said array for selectively activating each column of said array, said analog signal being directly coupled to said array to supplying said signal to the cells of said array, each of said cells comprising a first, capture section responsive to said row and column clock means for capturing one of said sample values at high speed, a storage section for holding said captured sample value for a relatively longer period than said capture section, an output buffer for transferring said captured sample to said analog signal output means, and transfer means for transferring said captured sample from said capture section to said storage section, whereby a very high speed sample of said analog signal may be taken by said capture section, said sample thereafter being transferred to said storage section.
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Abstract
An analog integrated circuit is disclosed using integrated field effect transistor technology comprising a plurality of sampling and storage cells. A two-stage sampling cell design is used. The first stage incorporates a very small capacitor coupled to the input signal through a high speed gate. This gate, which is opened only by the simultaneous occurrence of row and column cells in the circuit, causes this first capacitor to capture at very high speed a sample of the analog signal under study. When all the first capture sections of the cell have captured on their capacitors a sample of the analog signal, a transfer gate is briefly opened to transfer the captured and buffered sample values to the second or storage section of the cells. This storage section incorporates a capacitor substantially larger than the capacitor in the capture section, and capable of storing the signal for a considerably longer time.
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18 Claims
- 1. A high speed data acquisition system for storing a succession of sampled values of an analog signal comprising analog signal input means and analog signal output means, a first analog bus connected to said input means and a second analog bus connected to said output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said array for selectively activating each row of said array, column clock means coupled to said array for selectively activating each column of said array, said analog signal being directly coupled to said array to supplying said signal to the cells of said array, each of said cells comprising a first, capture section responsive to said row and column clock means for capturing one of said sample values at high speed, a storage section for holding said captured sample value for a relatively longer period than said capture section, an output buffer for transferring said captured sample to said analog signal output means, and transfer means for transferring said captured sample from said capture section to said storage section, whereby a very high speed sample of said analog signal may be taken by said capture section, said sample thereafter being transferred to said storage section.
Specification