Low voltage transient current limiting circuit

• US 4,924,342 A
• Filed: 08/03/1988
• Issued: 05/08/1990
• Est. Priority Date: 01/27/1987
• Status: Expired due to Term

• Current Assignee: Power Paragon, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: Teledyne Inet
• Inventors: Lee, Robert H.
• Primary Examiner(s): PELLINEN, A DAVID
• Assistant Examiner(s): Wysocki, A. Jonathan
• Application Number:
  US07/228,829
• Time in Patent Office: 643 Days
• Field of Search: 361/20, 361/21, 361/22, 361/42-50, 361/58, 361/111, 361/114, 361/115, 361/117, 361/91, 361/87
• US Class Current: 361/58
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: H02H 9/02 responsive to excess current current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025
• CPC Class Codes: Y10S 174/17 in an electric power conversion, regulation, or protection system

Abstract

A polyphase AC current limiting circuit, which incorporates improvements in control methods and circuitry that operate to avoid high rates of current change which occur upon initiation of a branch load fault and when the branch load fault is suddenly cleared. This "soft" start and "soft" load-off characteristic, reduces the voltage transients imposed on the AC power source and bus to relative insignificance compared with the voltage transients imposed by prior art current limiting circuits. The invention AC current limiting circuit comprises a high impedance circuit connected in parallel with a low impedance circuit, a load-off circuit connected in shunt with the device output power lines, and a control means for controlling the switching devices. When a branch load fault is sensed, the control means turns off the switches in the low impedance circuit through which normal current flows, and turns on the switches in the high impedance circuit, starting phased back, so that the initial current step is typically 100 percent of rated load current. Within a few cycles, the switches are phased to full on and the maximum current is limited by an inductor in series with the switches in the high impedance circuit. When the load fault is suddenly cleared and current drops to zero, the load-off circuit is energized and current continues to flow at graduated lower levels until the circuit is switched off. In the event that the load fault does not clear, the switches in the high impedance circuit are turned off, stopping current flow and a trip signal is transmitted to trip open an external input circuit breaker.

Claims

1. A method of controlling a polyphase AC current limiting circuit to produce in response to a load fault, a gradual rise in fault current at a rate typically less than 0.3 amperes per microsecond, so as to avoid the imposition of significant voltage transients on the AC electrical power bus;

the method comprising;

(a) connecting in each phase, a high impedance circuit which comprises two inverse-paralleled SCR'"'"'s in series with an inductor L1, across a low impedance circuit which comprises two inverse-paralleled GTO thyristors;

(b) detecting an overcurrent condition when load current rises sharply above a set pickup level;

(c) switching to "OFF" said GTO thyristors in said low impedance circuit, immediately upon detection of said overcurrent condition;

(d) switching to "ON", at the same time as Step (c), said SCR'"'"'s in said high impedance circuit;

said SCR'"'"'s being initially set at a retarded firing angle in the range of 85 to 130 degrees;

(e) changing the retarded firing angle of said SCR'"'"'s in said high impedance circuit, to reach zero degrees over a preset period of time or number of cycles and to phase said SCR'"'"'s full "ON"; and

(f) limiting the fault current in said high impedance circuit to a value which is determined by selection of said inductor L1.

2. A method of controlling a polyphase AC current limiting circuit to achieve a soft turn-off when fault current is removed, by causing a current to continue to flow in said current limiting circuit immediately upon clearing of the fault, and then reducing the current in steps to zero so as to avoid the imposition of significant voltage transients on the AC electrical power bus;

the method comprising;

(a) connecting to each output phase, a first, second and third inductor, designated L2, said inductors being connected to branches of a three phase SCR bridge circuit;

(b) detecting fault clearance when fault current is reduced sharply;

(c) switching the SCR'"'"'s to "ON" in said SCR bridge circuit immediately upon detection of said fault clearance;

said SCR'"'"'s being initially set at a retarded firing angle of zero degrees, allowing current to continue flowing through said L2 inductors and said SCR'"'"'s at about 40 to 50 percent below the maximum fault current level; and

(d) changing the retarded firing angle of said SCR'"'"'s in said SCR bridge circuit to reach 180 degrees over a preset period of time or number of cycles, resulting in zero current flow.

3. A method of controlling a polyphase AC current limiting circuit to achieve a soft turn-off when fault current is removed, by causing a current to continue to flow in said current limiting circuit immediately upon clearing of the fault, and then reducing the current in steps to zero so as to avoid the imposition of significant voltage transients on the AC electrical power bus;

the method comprising;

(a) connecting to each output phase, a line connecting to a branch of a three phase SCR bridge circuit;

there being a load resistor connected across said SCR bridge circuit;

(b) detecting fault clearance when fault current is reduced sharply;

(c) switching the SCR'"'"'s "ON" in said SCR bridge circuit immediately upon detection of said fault clearance;

said SCR'"'"'s being initially set at a retarded firing angle of zero degrees, allowing current to continue flowing through said SCR'"'"'s and said load resistor at about 40 to 50 percent below the maximum fault current level; and

(d) changing the retarded firing angle of said SCR'"'"'s in said SCR bridge circuit to reach 180 degrees over a preset period of time or number of cycles, resulting in zero current flow.

4. A method of protecting the dissipating elements in the high impedance circuit of a current limiting circuit from overheating due to continuing load fault current;

the method comprising;

(a) switching to "OFF" the SCR'"'"'s in said high impedance circuit; and

(b) if said SCR'"'"'s do not switch "OFF" due to failure, then activating the shunt trip circuit of the branch circuit breaker, causing it to trip open, disconnecting power from said current limiting circuit and thereby from said dissipating elements.

5. An improved polyphase AC current limiting circuit for the purpose of limiting fault current drawn by a faulted branch load, said fault current amplitude capable of causing significant voltage transients on the AC power bus that supplies said branch load;

said current limiting circuit comprising in combination;

(a) a low impedance power circuit in each phase, said low impedance power circuit comprising two Gate-Turn-Off (GTO) thyristors connected in inverse parallel, said GTO thyristors capable of being switched open in response to a gate control signal within a few microseconds at any electrical degree angle during an AC current cycle, and controlling the flow of current to the load;

(b) a high impedance power circuit in each phase, which is connected across said low impedance circuit, said high impedance power circuit for the purpose of providing a path for AC load fault current when said GTO thyristors in said low impedance power circuit are switched open;

said high impedance power circuit comprising two Silicon Control Rectifier (SCR) thyristors connected in inverse parallel and in series with a first inductor, said inductor selected to let-through a preset maximum fault current;

said SCR thyristors responsive to phase control signals from a control source;

(c) a current transformer connected in each input power phase line, said current transformer for the purpose of signalling the status of current flow to the control means;

(d) a three phase SCR bridge circuit, the branches of said SCR bridge circuit being connected in shunt with each output power phase line by shunt power lines;

each said shunt power line including a second inductor connected in series;

said second inductor selected to let-through a preset amplitude of current corresponding to approximately half the preset maximum fault current;

the SCR thryistors in said SCR bridge circuit and said second inductors being for the purpose of providing continuing current flow and limiting the rate of change in current when fault current is removed, thereby limiting the voltage transient caused by fault clearing to an arbitrarily low value;

(e) a control means, for monitoring the rate of change in load current, providing a control signal to the gates of said GTO thyristors in said low impedance power circuits to turn said GTO'"'"'s off when necessary;

for providing when necessary a control signal to the gates of said SCR thyristors in said high impedance power circuit, providing phase control drive to operate said SCR'"'"'s at a retarded firing angle of from 130 degrees to zero degrees over a preset period of time;

for providing when necessary, a control signal to the SCR gates of said three phase SCR bridge circuit, providing phase control drive to operate said SCR bridge circuit at a retarded firing angle starting from zero degrees to 180 degrees over a preset period of time; and

providing when necessary, a signal to energize an external shunt trip circuit of the external circuit breaker connecting said AC power bus to the input power lines of said AC current limiting circuit;

said control means comprising logic and control circuits for performing the foregoing control functions; and

(f) a logic power supply for providing regulated DC power for all said logic and control circuits in said control means.

6. The apparatus as defined in claim 5 wherein:

said control means includes a load current monitoring circuit, an overcurrent detector, GTO thyristor drive logic and drive circuits, SCR thyristor drive logic and drive circuits, SCR bridge drive logic and drive circuits, and circuit breaker trip logic and trip-circuit;

said load current monitoring circuit comprising three rectifier bridges, the branches of each said rectifier bridge being connected to said current transformers in each said input power phase line;

said rectifier bridges being connected in series with each other, the total output current of said rectifier bridges always being the highest instantaneous current of any individual phase current transformer, and passed through a loading resistor which is connected across said three rectifier bridges, developing a voltage signal that is proportional to the maximum current in any one of the three phases;

said over-current detector comprising a current reference circuit and a comparator-amplifier, said voltage signal across said loading resistor being coupled to said current reference circuit and input to said comparator-amplifier which compares said voltage signal with a reference from said current reference and outputs a current status signal High or Lo;

said GTO thyristor drive logic having an input connected to said current status signal from said comparator-amplifier, and having a timing circuit that processes said current status signal, outputting a drive shut off signal to the GTO drive circuit if said current status signal is High and continues for approximately 25 microseconds, causing said GTO'"'"'s in said low impedance power circuit to switch off;

said SCR thyristor drive logic having an input connected to said current status signal from said comparator-amplifier, and outputting an "ON" signal to said SCR thyristor drive circuit if said current status signal is High;

said SCR thyristor drive logic providing phase control drive to said SCR thyristors in said high impedance power circuit, varying said phase control retarded firing angle settings over a preset period of time;

said SCR bridge drive logic having an input connected to said current status signal from said comparator-amplifier, and on receipt of a Lo signal following a High signal, outputting an "ON" signal to said SCR bridge drive circuit;

said SCR bridge drive logic providing phase control drive to said SCR bridge thyristors, varying said phase control retarded firing angle settings over a period of time;

said circuit breaker trip logic having an input connected to said current status signal from said comparator amplifier, said status signal, if High, starting a timing sequence in a timing circuit and after a predetermined time interval, outputting a signal that energizes said breaker trip circuit, commanding the circuit breaker to trip open.

7. The apparatus as defined in claim 5 wherein:

said three phase SCR bridge circuit, as an alternate configuration, is connected directly in shunt with each output power phase line, without a second inductor connected in series;

said SCR bridge circuit having connected across it a loading resistor that is selected to let through a preset amplitude of current corresponding to approximately half the preeset maximum fault current;

the SCR thyristors in said SCR bridge circuit being responsive to control signals;

said SCR bridge circuit and said loading resistor being for the purpose of providing continuing current flow and limiting the rate of change in current when fault current is removed, thereby limiting the voltage transient caused by fault clearing to an arbitrarily low value.