Direct memory access controller with direct memory to memory transfers

• US 4,924,427 A
• Filed: 10/07/1988
• Issued: 05/08/1990
• Est. Priority Date: 11/15/1985
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Savage, Shaun V., Harris, Johnny M.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/255,076
• Time in Patent Office: 578 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/26
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer

Abstract

In a data processing system, each direct memory access controller is connected to a bus and the memory it controls, the memory being connected to a bus, bypassing the controller. The controller simultaneously generates two addresses, one for addressing the memory space it controls and another for addressing memory space controlled by another controller. Data is then passed directly from one memory space over the bus to another memory space in a single clock cycle. When a controller is acting as a bus master it causes the generation of a system, user or external signal signifying what memory space it will be permitted to access and each controller includes comparison circuits for comparing an address on the bus with one or more address space limit values, depending upon which of the three signals is received. An error signal is produced by the controller if another controller attempts to address memory space which it is not permitted to access. The controller also includes registers for storing an interrupt address, a constant value and status, and circuitry for transferring the status and constant value over the bus for storage at the interrupt address, the transfer taking place automatically upon detection of an exception.

Claims

1. A data processing system including:

first and second memory means, each having a plurality of addressable data storage locations;

a bus interconnecting said first and second memory means;

a first controller connected to said bus and said first memory means;

a second controller connected to said bus and said second memory means;

first means in said first controller for simultaneously generating the address of a first location in said first memory means and placing on said bus an address for addressing a second location in said second memory means;

first memory addressing means in said first controller responsive to said generated address for addressing said first memory means; and

,

second means in said second controller responsive to said address placed on said bus for addressing said location in said second memory means at the same time said first addressing means addresses said first location in said first memory means,

whereby a transfer of data takes place directly between an addressed location in said first memory means and an addressed location in said second memory means over said bus.

2. A data processing system as claimed in claim 1 wherein said first means comprises two counters, and means for incrementing said counters after each transfer of data so that succeeding data transfers take place between respective succeeding addressable data storage locations in said first and second memory means.

3. A data processing system as claimed in claim 2 wherein said second controller includes third means for simultaneously generating the address of a third location in said second memory means and placing on said bus an address for addressing a fourth location in said first memory means, said second controller including a second memory addressing means responsive to the said generated address of said third location for addressing said second memory means, said first controller including fourth means responsive to said address placed on said bus by said second controller for addressing said fourth location at the same time said second memory means addresses said third location.

4. A data processing system as claimed in claim 2 wherein said means for incrementing said counters comprises applying cyclic clock pulse to said counters whereby each transfer of data between said first and second memory means takes place during clock pulse cycle.

5. A data processing system as claimed in claim 1 and further comprising means in said first controller for generating a signal to control the direction of said data transfer between said first and second memory means.

6. A data processing system as claimed in claim 3 wherein said first and second controllers each include means producing a signal to initiate a direct memory access cycle;

bus arbitration means responsive to said signals for granting control of said bus to one of said first and second controllers;

a block counter in each of said first and second controllers;

means for incrementing the block counter with said clock pulses in the controller granted control of said bus, said block counter producing an output signal after each N clock pulses to initiate an operation of said bus arbitration means, N being an integer.

9. A data processing system as claimed in claim 1 wherein said first and second memory means are connected directly to said bus by transceiver means whereby said data transfer is accomplished without passing said data through said first or said second controller.

7. A data processing system including:

first and second memory means, each having a plurality of addressable data storage locations;

a bus interconnecting said first and second memory means;

a first controller connected to said bus and said first memory means;

a second controller connected to said bus and said second memory means;

first means in said first controller for simultaneously generating the address of a first location in said first memory means and placing on said bus an address for addressing a second location in said second memory means;

said first controller including means for producing a read/write signal;

first memory addressing means in said first controller responsive to said generated address and said read/write signal for addressing said first memory means to write data therein from said bus; and

,

second means in said second controller responsive to said read/write signal and said address placed on said bus for addressing said second location in said second memory means to read data therefrom to said bus at the same time said first addressing means addresses said first location in said first memory means,

whereby a transfer of data takes place directly from an addressed location in said second memory means to an addressed location in said first memory means.

10. A data processing system as claimed in claim 7 wherein said first and second memory means are connected directly to said bus by transceiver means whereby said data transfer is accomplished without passing said data through said first or said second controller.

8. A data processing system including:

first and second memory means, each having a plurality of addressable data storage locations;

a bus interconnecting said first and second memory means;

a first controller connected to said bus and said first memory means;

a second controller connected to said bus and said second memory means;

first means in said first controller for simultaneously generating the address of a first location in said first memory means and placing on said bus an address for addressing a second location in said second memory means;

said first controller including means for producing a read/write signal;

first memory addressing means in said first controller responsive to said generated address and said read/write signal for addressing said first memory means to read data therefrom to said bus; and

,

second means in said second controller responsive to said read/write signal and said address placed on said bus for addressing said second location in said second memory means to write data therein from said bus at the same time said first addressing means addresses said first location in said first memory means,

whereby a transfer of data takes place directly from an addressed location in said first memory means to an addressed location in said second memory means.

11. A data processing system as claimed in claim 8 wherein said first and second memory means are connected directly to said bus by transceiver means whereby said data transfer is accomplished without passing said data through said first or said second controller.