Static timing analysis of semiconductor digital circuits

• US 4,924,430 A
• Filed: 01/28/1988
• Issued: 05/08/1990
• Est. Priority Date: 01/28/1988
• Status: Expired due to Fees

• Current Assignee: Duet Technologies, Inc. (Tech Mahindra Limited)
• Original Assignee: Teradyne Incorporated
• Inventors: Choy, Kenneth C., Parham, Darrell R., Zasio, John J.
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/149,555
• Time in Patent Office: 831 Days
• Field of Search: 364/578, 364/488, 364/489, 364/490, 364/491, 371/23
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Claims

1. A method of verifying time-oriented operating requirements of a logic circuit including logic elements that are to be fabricated as semiconductor circuits to operate with propagation delays therethrough on applied data and clock signals that are correlated within predetermined ranges of timing parameters, the method comprising the steps of:

designating for each of the logic elements the absolute fast and relative slow extremes of one range of propagation delays therethrough;

designating for each of said logic elements the relative fast and absolute slow extremes of another range of propagation delays therethrough;

tracing selected data signal paths including logic elements through the logic circuit;

tracing selected clock signal paths through the logic circuit to selected logic elements;

accumulating the propagation delays at said absolute fast, relative slow, relative fast and absolute slow extremes of said ranges for logic elements along both the selected clock path and data signal path;

comparing the accumulated absolute fast path values to the relative slow path values of one range of propagation delays of the respective clock and data paths through the selected logic elements to determine the correlation of said absolute fast path values and said relative slow path values within a predetermined range of timing parameters; and

comparing the accumulated relative fast path values to the absolute slow path values of another range of propagation delays of the respective clock and data paths through the selected logic elements to determine the correlation of said relative fast path values and said absolute slow path values within a predetermined range of timing parameters.

2. The method according to claim 1 comprising the steps of identifying each of the logic elements for which the accumulated values of propagation delays in the clock and data signals along the selected respective clock and data signal paths to such logic element do not correlate within the predetermined range of timing parameters;

and

back-tracing along each of the selected clock and data signal paths from each such logic element to identify preceeding logic elements and the associated clock and data signal propagation delays associated therewith along said paths.

3. The method according to claim 1 wherein a selected logic element operates upon applied clock and data signals which are correlated within a required SET-UP interval, the method comprising in the step of accumulating the propagation delays at said relative slow and absolute slow extremes, accumulating the longest propagation delays along the selected data signal path;

in the step of accumulating the propagation delays at said absolute fast and relative fast extremes, accumulating the shortest propagation delays along the selected clock signal path;

in the step of comparing, comparing the accumulated absolute slow propagation delay of data signals along the selected data path with the accumulated relative fast propagation delay of clock signal along the selected clock signal path to said selected logic element for correlation thereof within said required SET-UP interval; and

comparing the accumulated relative slow propagation delay of data signals along the selected data path with the accumulated absolute fast propagation delay of the clock signal along the selected clock signal path to said selected logic element for correlation thereof within said required SET-UP interval.

4. The method of verifying time-oriented operating requirements of a logic circuit according to claim 3 in which the elements are to be fabricated as semiconductor circuits with connections therebetween that include skew propagation delay over the length thereof, the method comprising in the step of accumulating the propagation delays at said relative slow and absolute slow extremes, accumulating the longest propagation delays including the skew propagation delays of connections along the selected data signal path;

and

in the step of accumulating the propagation delays at said absolute fast and relative fast extremes, accumulating the shortest propagation delays excluding the skew propagation delays along the selected clock signal path.

5. The method according to claim 1 wherein a selected logic element operates upon applied clock and data signals which are correlated within a required HOLD interval, the method comprising in the step of accumulating the propagation delays at said absolute fast and relative fast extremes, accumulating the shortest propagation delays along the selected data signal path;

in the step of accumulating the propagation delays at said relative slow and absolute slow extremes, accumulating the longest propagation delays along the selected clock signal path; and

in the step of comparing, comparing the accumulated absolute fast propagation delay of data signals along the selected data path with the accumulated relative slow propagation delay of clock signal along the selected clock signal path to said selected logic element for correlation thereof within said required HOLD interval, and comparing the accumulated relative fast propagation delay of data signals along the selected data path with the accumulated absolute slow propagation delay of the clock signal along the selected clock signal path to said selected logic element for correlation thereof within said HOLD interval.

6. The method of verifying time-oriented operating requirements of a logic circuit according to claim 5 in which the elements are to be fabricated as semiconductor circuits with connections therebetween that include skew propagation delay over the lengths thereof, the method comprising in the step of accumulating the propagation delays at said relative fast and absolute fast extremes, accumulating the shortest propagation delays excluding the skew propagation delays of connections along the selected data signal path;

and

in the step of accumulating the propagation delays at said absolute slow and relative slow extremes, accumulating the longest propagation delays including the skew propagation delays along the selected clock signal path.

7. The method of verifying time-oriented operating requirements of a logic circuit according to claim 1 in which the logic elements are to be fabricated as a plurality of semiconductor circuit chips to operate with propagation delays therethrough on applied data and clock signals that are correlated within predetermined ranges of timing parameters, wherein the method is performed independently for the logic elements on each circuit chip.

8. The method according to claim 7 in which the logic elements on individual semiconductor circuit chips are to be interconnected by conductors having skew propagation delay associated therewith, and wherein in the steps of accumulating propagation delays, the skew delays of the conductors are included in the accumulated delays along clock signal and data signal paths for the longest propagation delays and are excluded from the accumulated delays for the shortest propagation delays.

9. A method of verifying time-oriented operating requirements of a logic circuit including logic elements that are to be fabricated as semiconductor circuits to operate within a plurality of ranges of propagation delays therethrough on applied first and second signals that are correlated within predetermined ranges of timing parameters, the method comprising the steps of:

designating for each of the logic elements at least four extremes of propagation delays therethrough including absolute slow and relative fast and absolute fast and relative slow;

tracing selected first signal paths including logic elements through the logic circuit;

tracing selected second signal paths through the logic circuit to selected logic elements;

selectively accumulating the propagation delays at both absolute and relative extremes of ranges for each logic element along the selected first signal path;

selectively accumulating the propagation delays at both absolute and relative extremes of ranges for each logic element along the selected second signal path to the selected logic element; and

comparing the accumulated absolute slow and relative slow values of first signal propagation delays along the selected first signal path to the selected logic element with the accumulated respective relative fast and absolute fast values of second signal propagation delays along the selected second signal path to the selected logic element for correlation of respective accumulated absolute and relative values within each of the predetermined ranges of timing parameters for said logic element.

10. The method according to claim 9 wherein the step of selectively accumulating the propagation delays include:

accumulating only the absolute slow and relative slow propagation delays along the selected first signal path; and

accumulating only the relative fast and absolute fast propagation delays along the selected second signal path.

11. The method according to claim 10 wherein one of the first and second signal paths forms the clock signal path between logic elements and the other of the first and second signal paths forms the data path between logic elements.