Method of making and testing an integrated circuit

• US 4,924,589 A
• Filed: 05/16/1988
• Issued: 05/15/1990
• Est. Priority Date: 05/16/1988
• Status: Expired due to Term

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/194,596
• Time in Patent Office: 729 Days
• Field of Search: 437/8, 324/73 PC, 29/846, 29/832, 29/407, 29/593
• US Class Current: 438/6
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49764 with testing or indicating

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surfaces traces are then connected, by means of multiplexers, to a conventional tester signal processor.

Claims

1. A method of making an integrated circuit comprising the steps of:

testing simultaneously a plurality of individual logic units of said integrated circuit prior to interconnecting said logic units;

with each of the units being electrically isolated from the other units during the test and

interconnecting said logic units so as to render said integrated circuit operable.

2. The method of claim 1, wherein said step of testing said logic units is prior to the step of interconnecting any of said logic units.

3. The method of claim 1, further comprising the step of providing a flexible tester surface comprising a layer of silicon dioxide and having a thickness of less than 15 microns;

and

wherein said step of testing comprising the step of bringing the flexible tester surface into electrical contact with said logic units by fluid pressure means exerted on said tester surface.

4. The method of claim 1, further comprising the step of revising a net placement list of said integrated circuit by CAD means so as to include in said revised placement net list only those logic units that pass said testing.

5. The method of claim 1, further comprising the steps of:

interconnecting said logic units by a thin conductive film; and

patterning said film by Electron-beam means.

8. The method of claim 4, wherein the step of revising the net placement list routing includes recomputation of the metallization trace routing.

9. The method of claim 4, wherein the step of revising the net placement list includes selected localized changes of the metallization trace routing.

10. The method of claim 9 wherein the step of revising the net placement list is performed using a CAD rip-up router.

11. The method of claim 3, further comprising the step of providing the tester surface with probe points having a diameter of about 2 to 4 microns for electrically contacting the logic units.

12. The method of claim 3, further comprising the step of providing more than one thousand probe points on the tester surface.

13. The method of claim 1, further comprising the steps of:

providing a piezoelectric pressure cell located at a backside of the flexible tester surface; and

wherein the step of testing includes the step of providing a voltage to the piezoelectric pressure cell so as to bring the tester surface into electrical contact with said logic units.

15. The method of claim 3, further comprising the step of providing the flexible tester surface with a plurality of probe points having a spacing between the centers of adjacent probe points equal to a spacing between contacts of one transistor in the integrated circuit.

16. The method of claim 15, wherein the spacing is less than about 15 μ

m between centers of adjacent probe points.

17. The method of claim 1, further comprising the steps of:

providing redundant logic units in each portions of the integrated circuit;

and wherein the step of interconnecting includes the step of interconnecting the redundant logic units with the adjacent individual logic units.

18. The method of claim 1, further comprising the step of providing a flexible tester surface;

and wherein said step of testing comprises the step of bringing the flexible tester surface into electrical contact with said logic units by pressure exerted on said flexible tester surface.

6. A method of making an integrated circuit comprising the steps of:

forming temporary interconnections between the logic units prior to testing;

testing individual logic units of said integrated circuit prior to interconnecting said logic units;

removing said temporary interconnections after testing; and

interconnecting said logic units so as to render said integrated circuit operable.

7. The method of claim 6, wherein said temporary interconnections are formed of a conductive layer and a dielectric layer.

14. The method of claim 7, wherein said temporary interconnections further are formed of a second conductive layer and a second dielectric layer, and said conductive layer and said second conductive layer are connected by electrically conductive vias.

19. A method of making an integrated circuit comprising the steps of:

providing contact pads for testing logic units, the contact pads each having a size of less than about 25 microns by 25 microns;

testing individual logic units of said integrated circuits by contacting said contact pads prior to interconnecting said logic units; and

interconnecting said logic units so as to render said integrated circuit operable.

20. The method of claim 19, wherein the contact pads have a size of about 4 microns by 4 microns.