Analog to digital conversion using correlated quantization and collective optimization

• US 4,926,180 A
• Filed: 03/25/1988
• Issued: 05/15/1990
• Est. Priority Date: 03/25/1988
• Status: Expired due to Term

• Current Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Original Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Inventors: Anastassiou, Dimitris
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Young, Brian K.
• Application Number:
  US07/173,441
• Time in Patent Office: 781 Days
• Field of Search: 341/155, 341/158, 341/159, 341/161, 341/166, 341/170, 341/200, 341/143, 341/122, 341/125, 364/513, 364/600, 364/602, 364/800, 364/801, 364/802, 364/807, 364/135, 364/178, 364/148, 364/149, 307/201, 365/49
• US Class Current: 341/159
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A 1-bit nonstandard A/D converter for converting a block u of N samples of a continuous time analog signal u(t) into N corresponding 1-bit binary values x, such that a distortion measure of the form d(u,x)=(Au-Bx)^T (Au-Bx) is minimized, is implemented with an N-input parallel sample-and-hold circuit and a neural network having N nonlinear amplifiers, where u and x are n-dimensional vectors, and A and B are N×N matrices. Minimization of the above distortion measure is equivalent to minimizing the quantity

1/2x.sup.T B.sup.T Bx-u.sup.T A.sup.T Bx,

which is achieved to at least a good approximation by the N-amplifier neural network. Accordingly, the conductances of the feedback connections among the amplifiers are defined by respective off-diagonal elements of the matrix -B^T B. Additionally, each amplifier of the neural network is connected to receive the analog signal samples through respective conductances defined by the matrix B^T. Furthermore, each amplifier receives a respective constant signal defined by the diagonal elements of the matrix -B^T B. The stabilized outputs of the N amplifiers are the binary values of the digital signal x.

A multiple-bit nonstandard A/D converter based on for foregoing 1-bit A/D converter is also disclosed.

Claims

1. A nonstandard analog-to-digital converter for converter a sampled analog signal u, having N samples u₁, . . . , u_N each with a value between a first and a second level, into a digital signal x, having N corresponding 1-bit binary values x₁, . . . , x_N, such that a distortion measure d=(Au-Bx)^T (Au-Bx) is minimized, where u and x are N-dimensional vectors, A and B are N×

N matrices, and N is an integer greater than 1, the converter comprising;

N nonlinear amplifying means A₁, . . . , A_N, each having an output terminal supplying an output signal and input means operatively coupled to receive the output signals supplied by other amplifying means, one or more of the analog signal samples and a respective constant signal, the input means for taking the weighted sum of the signals received thereby, including applying respective weighting factors to the received signals, and providing the weighted sum to the amplifying means, wherein for any two of the N amplifying means A_i and A_j, where i and j are independent integers having values i=1, 2, . . . N and j=1, 2, . . . , N, the weighting factor W_ij applied by the input means of A_i to the output signal supplied by A_j is the element of the i^th row and j^th column of a matrix -B^T B, the weighting factor K_ij applied by the input means of A_i to analog signal example u_j is the element of the i^th row and j_th column of a matrix B^T, the constant signal I_i received by the input means of A_i is the element of the i^th row and i^th column of the matrix -B^T B, and the output signal supplied by A_i operatively stabilizes to binary value x_i of the digital signal x.

2. An analog-to-digital converter according to claim 1, wherein each of the amplifying means has a sigmoid transfer function.

3. An analog-to-digital converter according to claim 2, wherein the input means of each amplifying means includes a plurality of resistance means.

4. An analog-to-digital converter according to claim 3, wherein the input means of each amplifying means A_i includes a resistance R_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of R_ij being proportional to 1/|W_ij |.

5. An analog-to-digital converter according to claim 4, wherein the input means of each amplifying means A_i further includes a resistance R_Iij corresponding to each weighting factor K_ij which is not equal to zero, the value of R_Iij being proportioned to 1/|K_ij |.

6. An analog-to-digital converter according to claim 5, wherein the input means of each amplifying means A_i further includes a resistance R_ci operatively coupled to a reference voltage V_R, the value of R_ci being proportional to V_R /I_i.

7. An analog-to-digital converter according to claim 2, wherein the input means of each amplifying means includes a plurality of switched capacitance means.

8. An analog-to-digital converter according to claim 7, wherein each amplifying means A_i includes a capacitance C coupled between the output terminal and an input node thereof, and the input means of each amplifying means A_i includes a capacitance C_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of C_ij being proportional to |W_ij |C.

9. An analog-to-digital converter according to claim 8, wherein the input means of each amplifying means A_i further includes a capacitance C_ij corresponding to each weighting factor K_ij which is not equal to zero, the value of C_ii being proportional to |K_ij |C.

10. An analog-to-digital converter according to claim 9, wherein the input means of each amplifying means A_i further includes a capacitance C_ci, the value of C_ci being proportional to |I_i |C.

11. A method for converting a discrete analog signal u, having N samples u₁, . . . , u_N each with a value between a first and a second level, into a digital signal x, having N corresponding 1-bit binary values x₁, . . . , x_N, such that a distortion measure d=(Au-Bx)^T (Au-Bx) is minimized, where u and x are N-dimensional vectors, A and B are N×

N matrices and N is an integer greater than 1, the method comprising the steps of;

providing N nonlinear amplifying means A₁, . . . , A_N, each receiving an input signal and supplying an output signal which is a sigmoid function of the input signal; and

forming the input signal for each amplifying means by weighting the output signals supplied by other amplifying means and one or more of the analog signal samples by applying respective weighting factors thereto and summing the weighted output signals, the weighted analog signal sample and a respective constant signal, wherein for any two of the N amplifying means A_i and A_j, where i and j are independent integers having values i=1, 2, . . . , N and j=1, 2, . . . , N, the weighting factor W_ij applied to the output signal supplied by A_j in forming the input signal for A_i is the element of the i^th row and j^th column of a matrix -B^T B, the weighting factor K_ij applied to the analog signal sample u_j in forming the input signal for A_i is the element of the i^th row and j^th column of a matrix B^T, the respective constant signal I_i of the input signal for A_i is the element of the i^th row and i^th column of the matrix -B^T B, and the output signal supplied by A_i operatively stabilizes to binary value x_i of the digital signal x.

12. A method according to claim 11, wherein the step of forming the input signal for each amplifying means A_i includes providing a resistance R_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of R_ij being proportional to 1/|W_ij |.

13. A method according to claim 12, wherein the step of forming the input signal for each amplifying means A_i includes providing a resistance R_Iij corresponding to each weighting factor K_ij which is not equal to zero, the value of R_ii being proportional to 1/|K_ij |.

14. A method according to claim 13, wherein the step of forming the input signal for each amplifying means A_i includes providing a reference voltage V_R and a resistance R_ci corresponding to the respective constant signal I_i, the value of R_ci being proportional to V_R /I_i.

15. A method according to claim 11, wherein the step of forming the input signal for each amplifying means A_i includes providing a capacitance C operatively coupled between an input and an output of A_i and switch capacitance means corresponding to each weighting factor W_ij and K_ij, the switched capacitance means corresponding to K_ij including a capacitance C_ij having a value proportional to |W_ij |C and the switched capacitance means corresponding to K_ij including a capacitance C_Iij having a value proportional to |K_ij |C.

16. A method according to claim 15, wherein the step of forming the input signal for each amplifying means A_i includes providing switched capacitor means corresponding to the respective constant signal I_i and including a capacitance C_ci having a value proportional to |I_i |C.

17. A nonstandard analog-to-digital converter for converting a discrete analog signal u having N samples u₁, . . . , u_N, into a digital signal x, having N corresponding m-bit binary values x₁, . . . , x_N, each equal to one of 2^m predefined quantization levels, such that a distortion functions d=[A(u-Q)-B(x'"'"'-Q)]² is minimized, where N and m are integers greater than 1, u and x'"'"' are N-dimensional vectors having values u₁, . . . , u_N and analog representations x'"'"'₁, . . . , x'"'"'_N of the binary values x₁, . . . , x_N, respectively, Q is an N-dimensional vector having first quantized values Q₁, . . . , Q_N equal to quantization levels closest to and smaller than corresponding samples of u, and A and B are N×

N matrices, the converter comprising;

truncating quantizer means operatively coupled to receive the analog signal samples u₁ . . . , u_N for providing the first quantized values Q₁, . . . Q_N and binary representations Q_b1, . . . Q_bN of the first quantized values;

analog subtraction means operatively coupled to receive the analog signal samples u₁, . . . , u_N and the first quantized values Q₁, . . . , Q_N for taking the difference between corresponding ones of the analog signal samples and the first quantized values to provide respective difference values u₁, . . . , u_N, where each difference value u_i is equal to u_i -Q_i for i=1, 2, . . . , N;

N nonlinear amplifying means A₁, . . . , A_N, each having an output terminal supplying an output signal and input means operatively coupled to receive the output signals supplied by other amplifying means, one or more of the difference values and a respective constant signal, the input means for taking the weighted sum of the signals received thereby, including applying respective weighting factors to the received signals and providing the weighted sum to the amplifying means, wherein for any two of the N amplifying means A_i and A_j, where i and j are independent integers having values i=1, 2, . . . , N and j=1, 2, . . . , N, the weighting factor W_ij applied by the input means of A_i to the output signal supplied by A_j is the element of the i^th row and j^th column of a matrix -B^T B, the weighting factor K_ij applied by the inputs means of A_i to u_j is the element of the i^th row and j^th column of a matrix B^T, and the respective constant signal I_i received by the input means of A_i is the element of the i^th row and i^th column of the matrix -B^T B; and

digital adder means coupled to receive the output signals supplied by the N amplifying means and the binary representations Q_b1, . . . , Q_bN of the first quantized values provided by the truncating quantizer means for summing the output signal supplied by each amplifying means A_i and the binary representation Q_bi corresponding to analog signal sample u_i to provide a binary value x_i of the signal x.

18. An analog-to-digital converter according to claim 17, wherein each of the amplifying means has a sigmoid transfer function.

19. An analog-to-digital converter according to claim 18, wherein the input means of each amplifying means includes a plurality of resistance means.

20. An analog-to-digital converter according to claim 19, wherein the input means of each amplifying means A_i includes a resistance R_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of R_ij being proportional to 1/|W_ij |.

21. An analog-to-digital converter according to claim 20, wherein the input means of each amplifying means A_i further includes a resistance R_Iij corresponding to each weighting factor K_ij which is not equal to zero, the value of R_Iij being proportional to 1/|K_ij |.

22. An analog-to-digital converter according to claim 21, wherein the input means of each amplifying means A_i further includes a resistance R_ci operatively coupled to a reference voltage V_R, the value of R_ci being proportional to V_R /I_i.

23. An analog-to-digital converter according to claim 18, wherein the input means of each amplifying means includes a plurality of switched capacitance means.

24. An analog-to-digital converter according to claim 23, wherein each amplifying means A_i includes a capacitance C operatively coupled between the output terminal and an input node thereof, and the input means of each amplifying means A_i includes a capacitance C_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of C_ij being proportional to |W_ij |C.

25. An analog-to-digital converter according to claim 24, wherein the input means of each amplifying means A_i further includes a capacitance C_Iij corresponding to each weighting factor K_ij which is not equal to zero, the value of C_Iij being proportional to |K_ij |C.

26. An analog-to-digital converter according to claim 25, wherein the input means of each amplifying means A_i further includes a capacitance C_ci, the value of C_ci being proportional to |I_i |C.

27. A method for converting a discrete analog signal u, having N samples u₁, . . . , u_N, into a digital signal x having N corresponding m-bit binary values x₁, . . . , x_N each equal to one of 2^m predefined quantization levels, such that a distortion function d=[A(u-Q)-B(x'"'"'-Q)]^T [A(u-Q)-B(x'"'"'-Q)] is minimized, where N and m are integers greater than 1, u and x'"'"' are N-dimensional vectors having values u₁, . . . , U_N and analog representations x₁ '"'"', . . . x_N '"'"' of the binary values x₁, . . . , x_N, respectively, Q is an N-dimensional vector having values Q₁, . . . , Q_N equal to quantization levels closest to and smaller than corresponding values of u, and A and B are N×

N matrices, the method comprising the steps of;

deriving N first quantized values Q₁, . . . , Q_N corresponding to the N analog signal samples u₁, . . . , u_N, each of the first quantized values being the quantization level closest to and smaller than its corresponding analog signal sample;

deriving N binary representations Q_b1, . . . , Q_bN of the first quantized values Q₁, . . . , Q_N ;

subtracting each of the first quantized values from its corresponding analog signal sample to obtain a difference value corresponding to the analog signal sample, where each difference value u_i is equal to u_i -Q_i for i=1, 2, . . . , N;

providing N nonlinear amplifying means A₁, . . . , A_N, each receiving an input signal and providing an output signal which is a sigmoid function of the input signal;

forming the input signal for each amplifying means by weighting the output signals supplied by other amplifying means and a respective one or more of the difference values by applying respective weighting factors thereto and summing the weighted output signals, the weighted difference values, and a respective constant signal, wherein for any two of the N amplifying means A_i and A_j, where i and j are independent integers having values i=1, 2, . . . , N and j=1, 2, . . . , N, the weighting factor W_ij applied to the output signal supplied by A_j in forming the input signal for A_i is the element of the i^th row and j^th column of a matrix -B^T B, the weighting factor K_ij applied to the difference value u_j in forming the input signal for A_i is the element of the i^th row and j^th column of a matrix B^T, the respective constant signal I_i of the input signal for A_i is the element of the i^th row and i^th column of the matrix -B^T B; and

summing the output signal supplied by each amplifying means A_i and binary representation Q_bi corresponding to analog signal sample U_i to obtain a corresponding binary value x_i of the digital signal x.

28. A method according to claim 27, wherein the step of forming the input signal for each amplifying means A_i includes providing a resistance R_ij corresponding to each weighting factor W_ij which is not equal to zero, the value of R_ij being proportional to 1/|W_ij |.

29. A method according to claim 28, wherein the step of forming the input signal for each amplifying means A_i includes providing a resistance R_Iij corresponding to each weighting factor K_ij which is not equal to zero, the value of R_Iij being proportional to 1/|K_ij |.

30. A method according to claim 29, wherein the step of forming the input signal for each amplifying means A_i includes providing a reference voltage V_R and a resistance R_ci corresponding to the constant signal I_i, the value of R_ci being proportional to V_R /I_i.

31. A method according to claim 27, wherein the step of forming the input signal for each amplifying means A_i includes providing a capacitance C operatively coupled between an input and an output of each amplifying means A_i and switch capacitance means corresponding to each weighting factor W_ij and K_ij, the switched capacitance means corresponding to W_ij including a capacitance C_ij having a value proportional to |W_ij |C and the switched capacitance means corresponding to K_ij including a capacitance C_Iij having a value proportional to |K_ij |C.

32. A method according to claim 31, wherein the step of forming the input signal for each amplifying means A_i includes providing switched capacitance means corresponding to the constant signal I_i and including a capacitance C_ci having a value proportional to |I_i |C.