Memory cartridge bank selecting

• US 4,926,372 A
• Filed: 05/05/1987
• Issued: 05/15/1990
• Est. Priority Date: 05/06/1986
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Nakagawa, Katsuya
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US07/047,039
• Time in Patent Office: 1,106 Days
• Field of Search: 364/200 MS File, 364/ 900 MS File, 364/707, 364/709
• US Class Current: 711/115
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory cartridge is loaded in a main unit of a personal computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other banks of the one-chip ROM.

Claims

1. A memory cartridge attachable and detachable from to a main unit including a computer, said main unit having a data bus, address bus, and a central processing unit, said memory cartridge comprising:

a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;

a first memory mounted on said circuit board and connected to said address lines and said data lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks; and

data holding means for holding said bank selecting data, said data holding means being mounted on said circuit board and connected to at least certain of said data lines and to said bank selecting input terminal of said first memory, said data holding means being loaded with bank selecting data read from said first memory in response to an enable signal for selecting or enabling said first memory and a write signal for writing data to said data holding means, such that said first memory is conditioned for reading data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data previously loaded into and held by said data holding means, wherein said first memory includes address terminals and said data holding means includes a semiconductor device which receives said bank selecting data from said first memory and sends a bank-switching signal to said address terminals, and wherein said semiconductor device is a counter.

2. A memory cartridge in accordance with claim 1, wherein said counter includes a gating means which, when provided with a signal produced by said central processing unit, directs this signal to the most significant of said address terminals of said first memory, and when not provided with this signal, directs an output of said holding means to the most significant of said address terminals of said first memory.

3. A memory cartridge attachable to and detachable from a data processing apparatus, said data processing apparatus having first and second data buses, first and second address buses, a central processing unit having limited addressing capability and being connected to said first data bus and said first address bus, and a video processing unit connected to said second data bus and said second address bus, said memory cartridge comprising:

a circuit board having first and second data lines attachable to said first and second data buses, respectively, and having first and second address lines attachable to said first and second address buses, respectively;

a first memory mounted on said circuit board and connected to said first data lines and said first address lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined addressable storage capacity exceeding that of the limited addressing capability of the central processing unit, said first memory being divided into a plurality of banks, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks adapted to store program data, at least one of said address locations of one of said banks adapted to store bank selecting data for selecting another of said banks;

a second memory connected to said second data lines and said second address lines, said second memory storing character data for video processing;

data holding means mounted on said circuit board for holding said bank selecting data, said data holding means having a data input terminal connected to at least certain of said first data lines, and having an output terminal; and

conductive pattern means formed on said circuit board and connecting said output terminal of said data holding means to said bank selecting input terminal of said first memory;

wherein

said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a write signal for writing of said data holding means, and said first memory reads out data stored in an address that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means, wherein said first memory includes address terminals, and said data holding means includes a semiconductor device which receives said bank selecting data from said first memory and sends a bank-switching signal to said address terminals, said semiconductor device comprises a counter means for holding said bank selecting data.

4. A memory cartridge in accordance with claim 3, wherein said counter includes a gating means which, when provided with a signal by said central processing unit, sends this signal to the most significant of said address terminals of said first memory, and when not provided with this signal, sends the output of said holding means to the most significant of said address terminals of said first memory.