Correction circuit for a digital quadrature-signal pair
First Claim
1. A correction circuit for a digital signal pair having an uncorrecting in-phase signal and an uncorrecting quadrature signal, comprising:
- an offset-correcting stage that receives said uncorrected in-phase signal and said uncorrected quadrature signal and that generates an offset-corrected in-phase signal and an offset-corrected quadrature signal, said offset-correcting stage further receiving an in-phase-offset-correcting signal and a quadrature-offset-correcting signal;
a phase-correcting stage that receives said offset-corrected in-phase signal and said offset-corrected quadrature signal and that generates an phase-corrected quadrature signal, said phase-correcting stage further receiving a phase-correcting signal;
an amplitude-correcting stage that receives said phase-corrected quadrature signal and that generates an amplitude-corrected quadrature signal, said amplitude-correcting stage further receiving an amplitude-correcting signal;
a value-determining stage comprising;
a first minimum detector that receives said offset-corrected in-phase signal and that generates an in-phase minimum value;
a first maximum detector that receives said offset-corrected in-phase signal and generates an in-phase maximum value;
a second minimum detector that receives said amplitude-corrected quadrature signal and generates a quadrature minimum value;
a second maximum detector that receives said amplitude-corrected quadrature signal and that generates a quadrature maximum value;
a first hold circuit that receives said amplitude-corrected quadrature signal, said first hold circuit responsive to said first minimum detector to store a first held quadrature value on the occurrence of said in-phase minimum value;
a second hold circuit that receives said amplitude-corrected quadrature signal, said second hold circuit responsive to said first maximum detector to store a second held quadrature value on the occurrence of said in-phase maximum value;
an error-detecting stage comprising;
a first adder that receives said in-phase maximum value from said first maximum detector and said in-phase minimum value from said first minimum detector, said first adder generating an in-phase offset error signal;
a second adder that receives said quadrature maximum value from said second maximum detector and said quadrature minimum value from said second minimum detector, said second adder generating a quadrature offset error signal;
a first subtracter having a minuend input that receives said second held quadrature value and having a subtrahend input that receives said first held quadrature value, said first subtracter generating a phase-error signal;
a second subtracter having a minuend input that receives said in-phase maximum value from said first maximum detector and having a subtrahend input that receives said in-phase minimum value from said first minimum detector, said second subtracter generating an in-phase amplitude value;
a third subtracter having a minuend input that receives said quadrature maximum value from said second maximum detector and having a subtrahend input that receives said quadrature minimum value from said second minimum detector, said third subtracter generating a quadrature amplitude value; and
a fourth substrater used as an amplitude comparator, said fourth subtracter having a minuend input that receives said quadrature amplitude value from said third subtracter and having a subtrahend input that receives said in-phase amplitude value from said second subtracter, said fourth subtracter generating an amplitude error signal; and
a first controller that receives said in-phase offset signal from said first adder and that generates said in-phase offset-correcting signal received by said offset-correcting stage;
a second controller that receives said quadrature offset error signal from said second adder and that generates said quadrature offset-correcting signal received by said offset-correcting stage;
a third controller that receives said phase-error signal generated by said first subtracter and that generates said phase-correcting signal received by said phase-correcting stage; and
a fourth controller that receives said amplitude-error signal generated by said fourth subtracter and that generates said amplitude-correcting signal received by said amplitude-correcting stage.
1 Assignment
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Accused Products
Abstract
A correction circuit for a digital signal pair having an in-phase signal and a quadrature signal includes a value determining stage and an error-detecting stage. The value-determining stage determines a maximum value and a minimum value for the in-phase signal, a maximum value and a minimum value for the quadrature signal, and two held values for the quadrature signal that correspond to the maximum and minimum values of the in-phase signal. These signals are used in the error-detecting stage to derive an in-phase offset error signal, a quadrature offset error signal, a phase-error signal, and an amplitude-error signal from which an in-phase-offset-correcting signal, a quadrature-offset-correcting signal, a quadrature phase-correcting signal, and quadrature amplitude-correcting signal are formed by associated controllers.
61 Citations
10 Claims
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1. A correction circuit for a digital signal pair having an uncorrecting in-phase signal and an uncorrecting quadrature signal, comprising:
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an offset-correcting stage that receives said uncorrected in-phase signal and said uncorrected quadrature signal and that generates an offset-corrected in-phase signal and an offset-corrected quadrature signal, said offset-correcting stage further receiving an in-phase-offset-correcting signal and a quadrature-offset-correcting signal; a phase-correcting stage that receives said offset-corrected in-phase signal and said offset-corrected quadrature signal and that generates an phase-corrected quadrature signal, said phase-correcting stage further receiving a phase-correcting signal; an amplitude-correcting stage that receives said phase-corrected quadrature signal and that generates an amplitude-corrected quadrature signal, said amplitude-correcting stage further receiving an amplitude-correcting signal; a value-determining stage comprising; a first minimum detector that receives said offset-corrected in-phase signal and that generates an in-phase minimum value; a first maximum detector that receives said offset-corrected in-phase signal and generates an in-phase maximum value; a second minimum detector that receives said amplitude-corrected quadrature signal and generates a quadrature minimum value; a second maximum detector that receives said amplitude-corrected quadrature signal and that generates a quadrature maximum value; a first hold circuit that receives said amplitude-corrected quadrature signal, said first hold circuit responsive to said first minimum detector to store a first held quadrature value on the occurrence of said in-phase minimum value; a second hold circuit that receives said amplitude-corrected quadrature signal, said second hold circuit responsive to said first maximum detector to store a second held quadrature value on the occurrence of said in-phase maximum value; an error-detecting stage comprising; a first adder that receives said in-phase maximum value from said first maximum detector and said in-phase minimum value from said first minimum detector, said first adder generating an in-phase offset error signal; a second adder that receives said quadrature maximum value from said second maximum detector and said quadrature minimum value from said second minimum detector, said second adder generating a quadrature offset error signal; a first subtracter having a minuend input that receives said second held quadrature value and having a subtrahend input that receives said first held quadrature value, said first subtracter generating a phase-error signal; a second subtracter having a minuend input that receives said in-phase maximum value from said first maximum detector and having a subtrahend input that receives said in-phase minimum value from said first minimum detector, said second subtracter generating an in-phase amplitude value; a third subtracter having a minuend input that receives said quadrature maximum value from said second maximum detector and having a subtrahend input that receives said quadrature minimum value from said second minimum detector, said third subtracter generating a quadrature amplitude value; and a fourth substrater used as an amplitude comparator, said fourth subtracter having a minuend input that receives said quadrature amplitude value from said third subtracter and having a subtrahend input that receives said in-phase amplitude value from said second subtracter, said fourth subtracter generating an amplitude error signal; and a first controller that receives said in-phase offset signal from said first adder and that generates said in-phase offset-correcting signal received by said offset-correcting stage; a second controller that receives said quadrature offset error signal from said second adder and that generates said quadrature offset-correcting signal received by said offset-correcting stage; a third controller that receives said phase-error signal generated by said first subtracter and that generates said phase-correcting signal received by said phase-correcting stage; and a fourth controller that receives said amplitude-error signal generated by said fourth subtracter and that generates said amplitude-correcting signal received by said amplitude-correcting stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification