Phase locked loop for clock extraction in gigabit rate data communication links

• US 4,926,447 A
• Filed: 11/18/1988
• Issued: 05/15/1990
• Est. Priority Date: 11/18/1988
• Status: Expired due to Term

• Current Assignee: Avago Technologies Fiber IP Singapore PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Nordby, Rasmus, Yen, Chu, Hornak, Tom, Walker, Rick C., Corsetto, Craig
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Bocure, T.
• Application Number:
  US07/273,302
• Time in Patent Office: 543 Days
• Field of Search: 375/95, 375/106, 375/110, 375/119, 375/120, 375/105.1, 370/105, 328/63, 328/74, 328/151, 328/155, 360/51
• US Class Current: 375/376
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A family of Phase Locked Loop circuits and methods for extraction of a clock signal from a digital data stream, for example as received by a data communication link receiver is taught. The circuits of this invention are particularly advantageous in gigabit rate links where the propagation delay of digital circuits is comparable to the duration of a bit time interval and therefore careful matching of clock extracting and data sampling circuit topology is required. In certain embodiments, a frequency detector is included making the structure suitable for use in situations where there is a large fractional difference between the incoming data rate and the free running frequency of the receiver VCO. Such is the case when both the incoming data rate and the receiver VCO frequency are not controlled by a precision element such as a crystal or a Surface Acoustic Wave device.

Claims

1. A structure for extracting a bit clock, a frame clock, and data from a data stream comprising:

an input port for receiving said data stream wherein;

said data stream is grouped into consecutive frames of N bits, where N is an integer,

each of said consecutive frames comprises at least two non-data bits, with two of said non-data bits being in consecutive bit positions and being of opposite logic values, the transition between said two non-data bits forming a master transition, said master transition being of the same polarity and located in the same position in each of said frames;

said consecutive frames are grouped into one or more groups of frames; and

an integral number of said consecutive frames at the beginning of each of said groups of frames constitute a training sequence comprising only said master transition and one transition of opposite polarity;

an output port for providing extracted data;

bit clock means for providing a bit clock signal which is adjusted in response to a binary clock control signal to match said data stream in frequency and phase;

a clock control source comprising;

an input lead connected to said input port;

a frame clock means for generating a frame clock signal having a frequency equal to 1/N times the bit clock signal frequency as means for selecting one of every 2N-th transition in said bit clock signal; and

an output lead supplying said binary clock control signal, said binary clock control signal changing its level at most once per frame, and having a first binary value when said selected bit clock transition occurred before said master transition and a second binary value when said selected bit clock transition occurred after said master transition, said binary clock control signal, when of said first binary value influencing said bit clock means to decrease the frequency of said bit clock and when of said second binary value influencing said bit clock means to increase the frequency of said bit clock; and

sampler means having an input lead connected to receive said data stream, a clock input lead for receiving said bit clock signal, and an output lead for providing said extracted data on said output port.

2. A structure as in claim 1 wherein said clock control source further comprises a phase detector having an input lead connected to said input port, a clock input lead for receiving said frame clock signal, and an output lead for providing said binary clock control signal.

3. A structure as in claim 2 wherein said sampler means comprises a first D flip flop, and said phase detector comprises a second D flip flop which is closely matched to said first D flip flop.

4. A structure as in claim 1 wherein said clock control source further comprises:

a phase detector having an input lead connected to said input port, a clock input lead for receiving said bit clock signal, and an output lead; and

a selector means having an input lead connected to said output lead of said phase detector, a clock input lead for receiving said frame clock signal, and an output lead for providing said binary clock control signal.

5. A structure as in claim 4 wherein said sampler means comprises a first D flip flop, and said phase detector comprises a second D flip flop which is closely matched to said first D flip flop.

6. A structure as in claim 4 wherein said selector means comprises a D flip flop.

7. A structure as in claim 4 wherein:

said selector means comprises;

a plurality of selection devices, each having an input lead, and output lead, and a clock input lead, said plurality of selection devices being connected in cascade with the input lead of the first of said selection devices serving as said input lead of said selector means and with the output lead of the last of said selection devices serving as said output lead of said selector means; and

a plurality of clock divider means, each having an input lead and an output lead, said plurality of clock divider means being connected in cascade with the input lead of the first clock divider means serving as said input lead of said frame clock means and with the output lead of the last clock divider means serving as said output lead of said frame clock means, each of said clock divider means providing an associated one of a plurality of divided clock signals, each of which is applied to the clock input lead of an associated one of said plurality of selection devices.

8. A structure as in claim 7 wherein said selection devices comprise D flip flops.

9. A structure as in claim 1 wherein said bit clock means comprises a voltage controlled oscillator.

10. A structure as in claim 1 wherein said clock control source receives said bit clock signal of a first phase and said sampler means receives said bit clock signal of a second phase.

11. A structure as in claim 10 wherein said first and second phases differ by approximately 180 degrees.

12. A structure as in claim 11 wherein said first and second phases have duty cycles of approximately 50%.

13. A structure as in claim 12 which further comprises a phase splitter having an input lead for receiving said bit clock signal, a first output lead for providing said bit clock signal of said first phase, and a second output lead for providing said bit clock signal of said second phase.

14. A structure as in claim 12 which further comprises:

a phase splitter having a first input lead for receiving said bit clock signal, a second input lead, a first output lead for providing said bit clock signal of said first phase, and a second output lead for providing said bit clock signal of said second phase;

differential amplifier means having a first input lead, a second input lead, and an output lead connected to said second input lead of said phase splitter;

a first low pass filter connected between said first output lead of said phase splitter and said first input lead of said differential amplifier means; and

a second low pass filter connected between said second output lead of said phase splitter and said second input lead of said differential amplifier means.

15. A structure as in claim 11 which further comprises a low pass filter for filtering said clock control signal.

16. A structure as in claim 15 which further comprises at least one phase modulator and a phase modulator signal source for controlling said at least one phase modulator.

17. A structure as in claim 16 wherein said phase modulator modulates said bit clock signal.

18. A structure as in claim 16 wherein said phase modulator modulates said first phase of said bit clock signal.

19. A structure as in claim 18 wherein said phase modulator is capable of modulating over a range centered at approximately 0 degrees.

20. A structure as in claim 17 wherein said first phase of said bit clock signal is provided by said phase modulator capable of modulating over a range centered at approximately 180 degrees.

21. A structure as in claim 16 which further comprises a first phase modulator which modulates said first phase of said bit clock signal, and a second phase modulator which modulates said second phase of said bit clock signal.

22. A structure as in claim 21 wherein said first and second phase modulators have substantially identical centers of modulating range.

23. A structure as in claim 22 which further comprises a low pass filter for filtering the signal from said phase modulator signal source before application to said second phase modulator.

24. A structure as in claim 16 wherein said phase modulator signal source comprises an integrator means having a first input lead connected to said input lead of said low pass filter, a second input lead connected to said output lead of said low pass filter, and an output lead connected to said at least one phase modulator.

25. A structure as in claim 18 which further comprises phase shift feedback means comprising:

a first input lead for receiving said bit clock signal of said first phase;

a second input lead for receiving said bit clock signal of said second phase; and

means for providing an output signal indicative of the difference in phase between said bit clock signals of first and second phase.

26. A structure as in claim 25 wherein said output signal indicative of the difference in phase between said bit clock signals of first and second phase serves as at least a portion of a phase modulator signal applied to said at least one phase modulator.

27. A structure as in claim 23 which further comprises phase shift feedback means comprising:

a first input lead for receiving said bit clock signal of said first phase;

a second input lead for receiving said bit clock signal of said second phase; and

means for providing an output signal indicative of the difference in phase between said bit clock signals of first and second phase.

28. A structure as in claim 27 wherein said output signal indicative of the difference in phase between said bit clock signals of first and second phase comprises at least a portion of a phase modulator signal applied to said second phase modulator.

29. A structure as in claim 15 which further comprises a frequency detector which serves to determine the sign of the difference between the frequency of said bit clock signal and the frequency of said data stream and cause said bit clock means to provide said bit clock signal having a frequency which is approximately equal to the frequency of said data stream.

30. A structure as in claim 29 wherein said frequency detector operates in response to a training sequence.

31. A structure as in claim 30 wherein said clock control source further comprises:

a first phase detector having an input lead connected to said input port, an output lead, and a clock input lead for receiving said frame clock signal as a means for selecting one of every 2N-th transition of said bit clock signal;

quadrature frame clock means for providing a quadrature frame clock signal having a frequency which is equal to the frequency of said frame clock signal but which is phase delayed from said frame clock signal by approximately a quarter of the period of said frame clock signal;

a second phase detector having an input lead connected to said input port, a clock input lead for receiving said quadrature frame clock signal, and an output lead for providing an output signal indicative of the logic level of said training sequence at a time specified by said quadrature frame clock signal;

a storage means having an input lead connected to the output lead of said first phase detector, a clock input lead connected to the output lead of said second phase detector, and an output lead for providing an output signal equal to the logic level of the output signal of said first phase detector at the time of a logic transition in the output signal of said second phase detector; and

switch means having a first input lead connected to said output lead of said first phase detector, a second input lead connected to said output lead of said storage means, a control input lead connected to said output lead of said second phase detector, and an output lead for providing said clock control signal, the signal on said control input lead causing said output lead of said switch means to be connected to said first input lead of said switch means when the logic level on said control input lead is of a first value and to be connected to said second input lead of said switch means when the logic level on said control input lead is of a second value.

32. A structure as in claim 31 wherein said output lead of said switch means is continuously connected to said first input lead of said switch means after lock has occurred but before the transmission of said training sequence is superseded by transmission of data.

33. A structure as in claim 30 wherein said clock control source further comprises:

a phase detector having an input lead connected to said input port, a clock input lead for receiving said bit clock signal, and an output lead;

first selector means having an input lead connected to said output lead of said phase detector, a clock input lead for receiving said frame clock signal as a means for selecting one of every 2N-th transition of said bit clock signal, and an output lead;

quadrature frame clock means for providing a quadrature frame clock signal having a frequency which is equal to the frequency of said frame clock signal but which is phase delayed from said frame clock signal by approximately a quarter of the period of said frame clock signal;

a second selector means having an input lead connected to said output lead of said phase detector, a clock input lead for receiving said quadrature frame clock signal, and an output lead for providing an output signal indicative of the logic level of said training sequence at a time specified by said quadrature frame clock signal;

a storage means having an input lead connected to said output lead of said first selector means, a clock input lead connected to said output lead of said second selector means, and an output lead for providing an output signal equal to the logic level of said output signal of said first selector means at the time of a logic transition in the output signal of said second selector means; and

switch means having a first input lead connected to said output lead of said first selector means, a second input lead connected to said output lead of said storage means, a control input lead connected to said output lead of said second selector means, and an output lead for providing said binary clock control signal, the signal on said control input lead causing said output lead of said switch means to be connected to said first input lead of said switch means when the logic level on said control input lead is of a first value and to be connected to said second input lead of said switch means when the logic level on said control input lead is of a second value.

34. A structure as in claim 33 wherein said output lead of said switch means is continuously connected to said first input lead of said switch means after lock has occurred but before the transmission of said training sequence is superseded by transmission of data.

35. A structure as in claim 20 wherein said low pass filter includes at least one pole and one zero.