Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor

• US 4,927,779 A
• Filed: 10/27/1989
• Issued: 05/22/1990
• Est. Priority Date: 08/10/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, Sang H., Lu, Nicky C., Henkels, Walter H.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): THOMAS, TOM
• Application Number:
  US07/428,159
• Time in Patent Office: 207 Days
• Field of Search: 437/38, 437/47, 437/52, 437/60, 437/203, 437/228, 437/919, 437/915, 357/23.6, 357/51, 365/188, 156/643, 156/644
• US Class Current: 438/153
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

Claims

1. A method for fabricating a memory cell for a semiconductor memory array comprising the steps of:

Step (1) disposed an epitaxial layer on a semiconductor substrate and reactive ion etch a trench into the said epitaxial layer and substrate,

Step (2) form a composite oxide/nitride/oxide storage insulator layer on the walls inside said trench,

Step (3) fill said trench with polysilicon and planarize,

Step (4) form a retrograde n-well in said epitaxial layer by a surface impurity implant and a deep impurity implant,

Step (5) grow gate oxide and deposit polysilicon gate material for a PMOS type device and deposit an oxide film insulator layer over the PMOS gate and lithographically pattern said oxide film layer,

Step (6) implant dopants into said n-well to provide graded source/drain junctions for PMOS and NMOS transistor devices, respectively,

Step (7) open the surfaces of said source/drain regions for silicide formation wherein said gate element is protected from said silicide by said oxide film insulator layer formed in step (5),

Step (8) form a lightly doped silicon film over said silicide, gate oxide and isolation regions wherein said lightly doped silicon film is deposited in polycrystalline structure and recrystallized by beam annealing,

Step (9) define the NMOS type transistor device active area and grow thin NMOS gate oxide,

Step (10) adjust channel threshold voltages by an impurity implant,

Step (11) deposit polysilicon NMOS type transistor device gate material and pattern,

Step (12) form oxide spacer regions on said NMOS gate electrode edges,

Step (13) implant dopants to obtain source/drain junctions for a transfer device and grow oxide to cover the device.

2. A method for fabricating a memory cell according to claim 1 wherein said substrate is composed of p+ type silicon, said epitaxial silicon layer is p type, said polysilicon filled in said trench in step (3) is p+ type, said n-well formed in step (2) is composed of a phosphorous implant and said source and drain regions of said PMOS and NMOS type transistor devices are formed of phosphorus and boron implants to provide graded source/drain junctions.

3. A method of fabricating a memory cell according to claim 1 wherein said lightly doped silicon film is deposited in polysilicon structure and the grain boundary traps are inactive by hydrogen passivation treatment.

4. A method of fabricating a memory cell according to claim 1 wherein said lightly doped silicon film is deposited amorphous film which is converted to single crystal by thermal treatment and with crystalline seeds of said silicided p+ source/drain region.

5. A method of fabricating a memory cell according to claim 1 wherein said lightly doped silicon is deposited in polycrysatalline structure and the p-type doping level is adjusted to provide a high threshold voltage.