Method and apparatus for encoding and decoding binary data
First Claim
1. Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions in order to effect high density data transmission comprising:
- means for converting each said data bit in series into a predetermined one of a plurality of code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and
means for transmitting each said code word from said conversion means.
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Abstract
An apparatus for encoding and decoding binary data in a data transmission system, such as a magnetic or optical medium data storage system is disclosed. The encoding process uses a modulation code wherein each data bit is encoded into a predetermined one of five code words, each code word including three code bits, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit. A "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition. In the process of decoding, each series of three code bits, defined with respect to a detected synchronization signal, are decoded using the inverse of the encoding process to convert the code bits back into data bits. The synchronization pattern generated during the encoding process includes at least ten successive "0" bits.
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Citations
28 Claims
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1. Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions in order to effect high density data transmission comprising:
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means for converting each said data bit in series into a predetermined one of a plurality of code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and means for transmitting each said code word from said conversion means. - View Dependent Claims (2, 3, 4)
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5. Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions recorded on a medium comprising:
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means for converting each said data bit in series into a predetermined one of four code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and means for recording each said code word at a successive location on said medium. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. Apparatus for receiving a series of signal transitions in a data transmission and for decoding binary data from said signal transitions comprising:
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means for detecting each said signal transition in said data transmission; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.
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19. In a system for storing binary bode bits stored on a medium as a series of signal transitions, an apparatus for decoding binary data from said signal transitions comprising:
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means for detecting each said signal transition on a selected segment of said medium; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.
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20. A state machine for encoding a series of input binary bit, with each input bit being converted into a 3-bit output code, comprising:
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a memory for storing five states for producing a 3-bit code in response to one of said binary bits, each state changing (C) or not changing (N) the polarity of a previous output bit, with a state I(NNC), state II(NNN), state III(NCN), state IV(NNN) and state V(CNN); means for sequencing through said states based on a present state and a next input bit such that for present state I, a next input 0 causes a transition to state II and a next input 1 causes a transition back to state I, for present state II, a next input 0 causes a transition to state III and a next input 1 causes a transition to state IV, for present state III, a next input 0 causes a transition back to state III and a next input 1 causes a transition to state IV, for present state IV, a next input 0 causes a transition to state V and a next input 1 causes a transition to state I, for present state V, a next input 0 causes a transition back to state V and a next input 1 causes a transition to state I. - View Dependent Claims (21, 22, 23, 24)
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25. A state machine for encoding a series of input binary bits, with each bit being converted to a 3-bit output for writing onto an optical media such that each "1" corresponds to a laser being turned on, comprising:
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a memory for storing states with said 3-bit codes, said states being state IA (000), state IB (100), state IIA (101), state IIB (000), state IIIA (000), state IIIB (001), state IVA (000), state IVB (010), and state VA (010), state VB (000); and means for sequencing through said states based on a present state and a next input bit such that present state IA, next input 0 goes to state IIA, 1 goes to state IB, present state IB, next input 0 goes to state IIB, 1 goes to state IA, present state IIA, next input 0 goes to state IIIA, 1 goes to state VA, present state IIB, next input 0 goes to state IIIB, 1 goes to state VB, present state IIIA, next input 0 goes to state IIIB, 1 goes to state IVA, present state IIIB, next input 0 goes to state IIIA, 1 goes to state IVB, present state IVA, next input 0 goes to state VA, 1 goes to state IA, present state IVB, next input 0 goes to state VB, 1 goes to state IB, present state VA, next input 0 goes to state VB, 1 goes to IB, present state VB, next input 0 goes to state VA, 1 goes to IA. - View Dependent Claims (26)
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27. A state machine for decoding a series of 3-bit corresponding to different states to produce an output binary bit stream, comprising:
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means for recognizing codes corresponding to state IA (001), state IB (110), state IIA (111), state IIB (000), state IIIA (100), state IIIB (011), state IVA (000), state IVB (111), state VA (111), state VB (000); and means for producing output bits upon transitions between states such that states IA to IB and IB to 1A produces 1, states IA to IIA and IB to IIB produces 0, states IIA to VA and IIB to VB produces 1, states IIA to IIIA and IIB to IIIB produces 0, states IIIA to IVA and IIIB to IVB produces 1, states IIIA to IIIB and IIIB to IIIA produces 0, states IVA to IA and IVB to IB produces 1, states IVA to VA and IVB to VB produces 0, states VA to IB and VB to IA produce 1, and states VA to VB and VB to VA produces 0. - View Dependent Claims (28)
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Specification