Multiple channel data acquisition system

• US 4,928,246 A
• Filed: 10/21/1988
• Issued: 05/22/1990
• Est. Priority Date: 10/21/1988
• Status: Expired due to Fees

• Current Assignee: Iowa State University Research Foundation Incorporated (Iowa State University)
• Original Assignee: Iowa State University Research Foundation Incorporated (Iowa State University)
• Inventors: Thomas, William D., Gorbics, Mark S., McKay, Roy L., Homer, John F. Jr., Rosenberg, Eli I., Meyer, W. Thomas, Crawley, H. Bert
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Mattson, Brian M.
• Application Number:
  US07/261,031
• Time in Patent Office: 578 Days
• Field of Search: 364/514, 364/550, 364/137, 364/138, 364/140, 364/148, 364/178, 364/179, 340/825.06, 340/825, 341/141, 341/142, 341/155
• US Class Current: 700/8
• CPC Class Codes: G01D 1/00 Measuring arrangements giving results other than momentary value of variable, of general application G01D3/00 takes precedence; in tariff metering apparatus G01D4/00; transducers not specially adapted for a specific variable G01D5/00

Abstract

A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory. The local processor executes programs which are downloaded to the module memory through the FASTBUS coupler.

Claims

1. A multiple channel data acquisition system for converting analog signals from a multiplicity of data channels into digital data samples and for transferring the data samples to a host processor, said data acquisition system comprising:

a plurality of data acquistion modules, each including a local processor means, module memory means, channel conversion means, front end buffer (FEB) means, and communications coupling means;

a high speed communication pathway which couples each communications coupling means of a respective module to the host processor;

each of said data acquisition modules further including a module bus for coupling said FEB means, said module memory means, said local processor means, and said communication coupling means, said module bus adapted for bidirectional communications between said FEB means and said module memory means, said FEB means and said communications coupling means, or said module memory means and said communications coupling means;

said channel conversion means including means for periodically converting the analog signals from at least one of said data channels into the data samples, cache memory means, means for storing the data samples in said cache memory means, and means for periodically transferring the data samples stored in said cache memory means to said FEB means;

wherein said host processor controls communications between said communications coupling means and said module memory means or said FEB means; and

wherein said local processor controls communications between said module memory means and said FEB means or said communications coupling means.

2. The multiple channel data acquisition system as set forth in claim 1 wherein said means for periodically transferring said data samples stored in said cache memory means to said FEB means includes:

means for processing said data samples in accordance with information contained in the data samples stored in said cache memory means.

3. The multiple channel data acquisition system as set forth in claim 2 wherein said means for processing includes:

means for compressing the data samples stored in said cache memory means.

4. The multiple channel data acquisition system as set forth in claim 3 wherein said means for compressing the data samples stored in said cache memory means includes:

means for discarding data samples which are less than a predetermined threshold value.

5. The multiple channel data acquisition system as set forth in claim 3 wherein said means for compressing the data samples stored in said cache memory means includes:

means for discarding data samples based upon information contained in two or more consecutive data samples.

6. The multiple channel data acquisition system as set forth in claim 5 wherein said means for discarding includes:

means for discarding data samples which are less than a predetermined threshold value or are not preceded by n data samples or followed by n data samples which are greater than or equal to said threshold value, n being an integer value or zero.

7. The multiple channel data acquisition system as set forth in claim 1 wherein said means for periodically transferring said data samples from said cache memory means to said FEB means comprises:

address generation means for reading data samples from said cache memory means at a read address and for writing data samples to said FEB mean at a write address.

8. The multiple channel data acquisition system as set forth in claim 7 wherein said address generation means includes:

means for comparing the digital value of a read data sample to an amplitude threshold;

means for incrementing the read address to read the next data sample;

means for incrementing the write address if the digital value of said compared data sample is greater than said threshold; and

storing the next data sample at the write address.

9. The multiple channel data acquisition system as set forth in claim 8 wherein said address generator means further includes:

means for storing said write address if said present data sample is greater than said amplitude threshold;

means for comparing the number of consecutive data samples thereafter in excess of a width threshold;

means for resetting said write address to said stored address if said comparison is not in excess of said width threshold.

10. The multiple channel data acquisition system as set forth in claim 9 which further includes:

amplitude threshold memory means for storing said amplitude threshold at a memory location corresponding to a particular data channel; and

width threshold memory means for storing said width threshold to a memory location corresponding to a particular data channel.

11. The multiple channel data acquisition system as set forth in claim 1 wherein:

said module memory means is partitioned into a program buffer means for storing instructions executable by said local processor means and a module event buffer means for storing data samples transferred from said FEB means; and

said local processor means includes means for executing said instructions stored in said program buffer means to control the transfer of said data samples from said FEB means to said module event buffer means.

12. The multiple channel data acquisition system as set forth in claim 11 wherein:

said program buffer means comprises random access memory which is addressable by said communications coupling means.

13. The multiple channel data acquisition system as set forth in claim 12 which further includes:

means for downloading said executable instructions through said communications coupling means to each module memory means.

14. The multiple channel data acquisition system as set forth in claim 11 wherein:

said module event buffer means comprises random access memory which is addressable by said communications coupling means.

15. The multiple channel data acquisition system as set forth in claim 14 which further includes:

means for uploading said stored data samples from each module event buffer through said communications coupling means.

16. The multiple channel data acquisition system as set forth in claim 11 wherein:

said local processor means includes means for executing said instructions stored in said program buffer means to process said data samples during transfer from said FEB means to said module event buffer means.

17. The multiple channel data acquisition system as set forth in claim 16 wherein:

said means for executing instructions processes said data samples into a format compatible with said host processor.

18. The multiple channel data acquisition system as set forth in claim 16 wherein:

said means for executing instructions processes said data samples according to a characteristic of the data.

19. The multiple channel data acquisition system as set forth in claim 18 wherein:

said means for executing instructions compresses said data samples based upon whether any data samples are stored in said FEB means.

20. The multiple channel data acquisition system as set forth in claim 19 wherein:

said means for executing instructions communicates with said uploading means to indicate whether any data samples have been transferred to said module event buffer means.

21. A method for converting the analog signals from a multiplicity of data channels into digital data samples and for transferring the data samples to a host processor, said method comprising:

sampling the multiplicity of data channels in parallel in response to a trigger signal by the host processor to generate the data samples;

storing the data samples of each channel into an associated multiplicity of first memories;

transferring said data samples from a plurality of channels stored in said first memories into an associated multiplicity of second memories;

processing said data samples into processed data samples during said transfer from said first to said second memories;

transferring said processed data samples from a plurality of second memories into an associated multiplicity of third memories;

processing said processed data samples into information samples during said transfer from said second to third memories; and

transferring said information samples from each of said third memories to said host processor.

22. The conversion method as set forth in claim 21 wherein said step of sampling includes:

sampling a plurality of sequential data samples during a load period of specific duration.

23. The conversion method as set forth in claim 22 wherein said step of transferring said data samples from said first memories to said second memories includes:

sequentially transferring all data samples from one channel before transferring the data samples of the next channel in the plurality of channels during a dump period of specific duration.

24. The conversion method as set forth in claim 23 wherein:

said step of sampling is accomplished at a higher rate than said step of transferring data samples from said first to second memories.

25. The conversion method as set forth in claim 23 wherein said step of transferring said processed data from said second to said third memories includes:

halting said processing step during said load and dump periods.

26. The conversion method as set forth in claim 23 wherein said step of processing said data samples includes:

compressing said data samples into fewer data samples.

27. The conversion method as set forth in claim 26 wherein said step of compressing includes:

discarding data samples which have less amplitude than a threshold.

28. The conversion method as set forth in claim 27 wherein said step of discarding includes:

writing said discarded data samples into said second memory;

determining whether said discarded data samples are less than said threshold;

overwriting said discarded data samples with data samples which are in excess of said threshold.

29. The conversion method as set forth in claim 26 wherein said step of compressing includes:

discarding data samples which have less width than a threshold.

30. The conversion as set forth in claim 21 wherein said step of processing said processed data samples includes:

formatting said information samples for transfer to said host processor.