Semiconductor integrated circuit
First Claim
1. A semiconductor integrated circuit comprising:
- (1) a memory matrix including a plurality of memory cells;
(2) address means for selecting at least one of said plurality of memory cells of said memory matrix in response to an address signal;
(3) a sense amplifier for amplifying a signal from said at least one selected memory cell;
(4) a first memory circuit having an input connected to the output of said sense amplifier;
(5) a second memory circuit having an input connected to the output of said sense amplifier; and
(6) a signal generator for generating a first control signal and a second control signal in response to changes in said address signal,wherein the timing of said first control signal is set to be different from the timing of said second control signal,wherein said first memory circuit fetches the output of said sense amplifier in response to said first control signal, andwherein said second memory circuit fetches the output of said sense amplifier in response to said second control signal.
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Accused Products
Abstract
Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
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Citations
9 Claims
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1. A semiconductor integrated circuit comprising:
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(1) a memory matrix including a plurality of memory cells; (2) address means for selecting at least one of said plurality of memory cells of said memory matrix in response to an address signal; (3) a sense amplifier for amplifying a signal from said at least one selected memory cell; (4) a first memory circuit having an input connected to the output of said sense amplifier; (5) a second memory circuit having an input connected to the output of said sense amplifier; and (6) a signal generator for generating a first control signal and a second control signal in response to changes in said address signal, wherein the timing of said first control signal is set to be different from the timing of said second control signal, wherein said first memory circuit fetches the output of said sense amplifier in response to said first control signal, and wherein said second memory circuit fetches the output of said sense amplifier in response to said second control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification