IC test system

• US 4,928,278 A
• Filed: 08/05/1988
• Issued: 05/22/1990
• Est. Priority Date: 08/10/1987
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Otsuji, Taiichi, Narumi, Naoaki
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Baker, Stephen M.
• Application Number:
  US07/229,780
• Time in Patent Office: 655 Days
• Field of Search: 371/15, 371/25, 371/27, 371/1, 324/73 AT, 364/579, 364/580, 364/571.01
• US Class Current: 714/700
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

Calibration of timing errors of each pin electronics unit is carried out by a main controller and a plurality of controllers, each assigned to each pin electronics unit or to each block including a plurality of pin electronics units. A reference timing signal is simultaneously distributed to each pin electronics unit or block, so that the timing error calibration is executed in parallel among the pin electronics units or the blocks.

Claims

1. An IC test system for testing an IC device by supplying a test signal pattern to said IC device through the input/output pins of said IC device and by receiving output signals froms aid IC device through said input/output pins, comprising:

(A) clock means for generating clocks;

(B) a main controller for controlling said IC test system;

(C) a plurality of pin electronics units, each of which is assigned to each of said input/output pins, each pin electronics unit having;

(C1) timing signal generating means for generating, in response to the clocks from said clock means, first timing signals for providing timings for supplying said test signal pattern to said IC device and a second timing signal for providing a timing for judging test result of said IC device;

(C2) pattern generating means for generating said test signals pattern in accordance with the timings defined by said first timing signals;

(C3) test result judging means receiving said test signal pattern and responses of said IC device to said test signal pattern and for judging the result of said responses at the timing of said second timing signal; and

(C4) a controller for cooperating with said timing signal generating means, said pattern generating means said test result judging means to measure errors of said first and second timing signals and an error of the length of a line between each pin electronics unit and its corresponding input/output pin and for performing arithmetic operations of and controls of calibration of said errors;

(D) reference timing signal generating means receiving the clock from said clock means and for generating a reference timing signal which defines a time reference when measuring said errors; and

(E) distributing means for simultaneously distributing, in the case of said calibration of said errors, said reference timing signal to said test result judging means of all said pin electronics units or to said test result judging means of all said pin electronics units and the input/output pins corresponding to respective ones of said plurality of pin electronics units;

said main controller controlling said clock means, said controller in each of said plurality of pin electronics units and said reference timing signal generating means to execute said calibration of said errors for said plurality of pin electronics units in parallel among said plurality of pin electronics units.

2. An IC test system as claimed in claim 1, wherein said pattern generating means includes a pattern generation circuit for storing therein pattern data for designating mode and level of said test signal pattern and a waveform formatter circuit receiving said first timing signals and said pattern data and for generating said test signal pattern.

4. An IC test system as claimed in claim 1, wherein said distributing means comprises a plurality of one-input/multi-output OR logic gates connected in the form of tree.

5. An IC test system as claimed in claim 1, wherein each of said pin electronics units includes a first switch having one terminal connected to said distributing means, a second switch having one terminal connected to said test result judging means and a third switch having one terminal connected to each of said input/output pins and the other terminals of said first, second and third switches are connected in common.

6. An IC test system as claimed in claim 1, wherein said pattern generating means includes a driver circuits for supplying said test signal pattern to said test result judging means.

3. An IC test system as claimed in clam 1, wherein said test result judging means includes a comparator for comparing said test signal pattern and said response to said test signal pattern with a comparison reference level at a timing of said second timing signal and a storage circuit for storing comparison results from said comparator.

7. An IC test system for testing an IC device by supplying a test signal pattern to said IC device through the input/output pins of said IC device and by receiving output signals from said IC device through said input/output pins, comprising:

(A) clock means for generating clocks;

(B) a main controller for controlling said IC test system;

(C) a plurality of pin electronics units, each of which is assigned to each of said input/output pins, each pin electronics unit having;

(C) timing signal generating means for generating, in response to the clocks from said clock means, first timing signals for providing timings for supplying said test signal pattern to said IC device and a second timing signal for providing a timing for judging test result of said IC device;

(C2) pattern generating means for generating said test signal pattern in accordance with the timings defined by said first timing signals; and

(C3) test result judging means receiving said test signal pattern and responses of said IC device to said test signal pattern and for judging the result of said responses at the timing of said second timing signal;

(D) a plurality of controllers, each assigned to each one of a plurality of blocks, each of which has a plurality of pin electronics units and for cooperating with said main controller, said timing signal generating means, said pattern generating means and said test result judging means to measure errors of said first and second timing signals and an error of the length of line between each pin electronics unit and its corresponding input/output pin and for performing arithmetic operations of and controls of calibration of said errors;

(E) reference timing signal generating means receiving the clocks from said clock means and for generating a reference timng signal which defines a time reference when measuring said errors; and

(F) distributing means for simultaneously distributing, in the case of said calibration of said errors, said reference timing signal to said test result judging means of all said pin electronics units in said plurality of blocks or to said test result judging means of all said pin electronics units in said plirality of blocks and said input/output pins corresponding to respective ones of said plurality of blocks;

said main controller controlling said clock means, said plurality of controllers and said reference timing signal generating means to execute said calibration of said errors for said plurality of pin electronics units in series with respect to said plurality of electronics units in each block and in parallel among said plurality of blocks.

8. An IC tests system as claimed in claim 7, wherein said pattern generating means includes a pattern generation circuit for storing therein pattern data for designating mode and level of said test signal pattern and a waveform formatter circuit receiving said first timing signals and said pattern data and for generating said test signal pattern.

9. An IC test system as claimed in claim 7, wherein said test result judgiing means includes a comparator for comparing said test signal pattern and said response to said test signal pattern with a comparison reference level at a timing of said second timing signal and a storage circuit for storing comparison results from said comparator.

10. An IC test system as claimed in claim 7, wherein said distributing means includes first distributing means provided in common to all of said plurality of blocks and a plurality of second distributing means, each provided in common to said plurality of pin electronics units in each of said plurality of blocks.

11. An IC test system as claimed in claim 10, wherein each of said first and second distributing means includes a plurality of one-input/multi-output OR logic gates connected in the form of tree.

12. An IC test system as claimed in claim 7, wherein said distributing means includes a plurality of one-input/multi-output OR logic gates connected in the form of tree.

13. An IC test system as claimed in claim 7, wherein each of said pin electronics units includes a first switch having one terminal connected to said distributing means, a second switch having one terminal connected to said test result judging means, a third switch having one terminal connected to each of said input/output pins and the other terminals of said first, second and third switches are connected in common.

14. An IC test system as claimed in claim 7 wherein said pattern generating means includes a driver circuit for supplying said test signal pattern to said test result judging means.

15. An IC test system for testing an IC device by supplying a test signal pattern to said IC device through the input/output pins of said IC device and by receiving output signals from said IC device through said input/output pins, comprising:

(A) clock means for generating clocks;

(B) a main controller for controlling said IC test system;

(C) a plurality of timing generating means, each assigned to each of said input/output pins, and each responsive to the clocks from said clock means for generating first timing signals for providing timings for supplying said second timing signal for providing a timing for judging test result of said IC device;

(D) a plurality of pattern generating means, each assigned to each of said input/output pins, and each for generating said test signal pattern in accordance with the timings defined by said first timing signals;

(E) a plurality of test result judging means, each assigned to each of said input/output pins, and each responsive to said test signal pattern and to responses of said IC device to said test signal pattern for judging the result of said responses at the timing of said second timing signal;

(F) a plurality of controllers, each cooperating with said main controller, said timig signal generating means, said pattern generating means and said test result judging means to measure errors of said first and second timing signals and an error of the length of a line between said IC test system and each of said input/output pins for performing arithmetic operations of and controls of said calibration of said errors;

(G) reference timing signal generating means receiving the clocks from said clock means and for generating a reference timing signal which defines a time reference when measuring said errors; and

(H) distributing means for simultaneously distributing, in the case of said calibration of said errors, said reference timing signal to said plurality of test result judging means or to said plurality of test result judging means and all of said input/output pins;

said main controller controlling said clock means;

said plurality of controllers and said reference timing signal generating means to execute said calibration of said errors in parallel among said plurality of controllers.

16. As IC test system as claimed in claim 15, wherein said pattern generating means includes a pattern generation circuit for storing therein the pattern data for designating mode and level of said test signal pattern and waveform formatter circuit receiving said first timing signals and said pattern data and for generating said test signal pattern.

17. An IC test system as claimed in claim 15, wherein said test result judging mean includes a comparator for comparing said test signal pattern and said response to said test signal pattern with a comparison reference level at a timing of said second timing signal and a storage circuit of storing comparison results from said comparator.

18. An IC test system as claimed in claim 15, wherein said distributing means includes a plurality of one-input/multi-output OR logic gates connected in the form of tree.

19. An IC test system as claimed in claim 15, wherein each of said pin electronics units includes a first switch having one terminal connnected to said distributing means, a second switch having one terminal connected to said test result judging means, a third switch having one terminal connected to each of said input/output pins and the other terminals of said first, second and third switch are connected in common.

20. An IC test system as claimed in claim 15, wherein said pattern generating means includes a driver circuit for supplying said test signal pattern to said test result judging means.

21. An IC test system for testing an IC device by supplying a test signal pattern to said IC device through the input/output pins of said IC device and by receiving output signals from said IC device through said input/output pins, comprising:

(a) clock means for generating clocks;

(B) a main controller for controlling said IC test system;

(C) common timing signal generating means for generating a common timing signal in response to the clock from said clock means;

(D) a plurality of timing adjusting means;

each assigned to each of said input/output pins, and for adjusting timing of said common timing signal to generate first timing signals for providing timings for supplying said test signal pattern to said IC device and a second timing signal for providing a timing for judging test result of said IC device;

(E) a plurality of pattern generating means, each assigned to each of said input/output pins, and for generating said test signal pattern in accordance with the timings defined by said first timing signals;

(F) a plurality of test result judging means, each assigned to each of said input/output pins, and each responsive to said test signal pattern and to responses of said IC device to said test signal pattern for judging the result of said responses at the timing of said second timing signal;

(G) a plurality of controllers, each for cooperating with said main controller, said timing signal adjusting means, said pattern generating means and said test result judging means to measure errors of said first and second timing signals and an error of the length of a line between said IC test system and each of said input/output pins for performing arithmetic operations of and controls of said calibration of said errors;

(H) reference timing signal generating means receiving the clocks from said clock means and for generating a reference timing signal which defines a time reference when measuring said errors; and

(I) distributing means for simultaneously distributing, in the case of said calibration of said errors, said reference timing signal to said plurality of test result judging means or to said plurality of test result judging means and all of said input/output pins;

said main controller controlling said clock means, said common timing signal generating means, said plurality of controllers and said reference timing signal generating means to execute said calibration of said errors parallel among said plurality of controllers.

22. An IC test system as claimed in claim 21, wherein said pattern generation means includes a pattern generation circuit for storing therein pattern data for designating mode and level of said test signal pattern and a waveform formatter circuit receiving said first timing signals and said pattern data and for generating said test signal pattern.

23. An IC test system as claimed in claim 21, wherein said test result judging means includes a comparator for comparing said test signal pattern and said response to said test signal pattern with a comparison reference level at a timing of said second timing signal and a storage circuit for storing comparison results from said comparator.

24. An IC test system as claimed in claim 21, wherein said distributing means inclides a plurality of one-input/multi-output OR logic gates connected in the form of tree.

25. An IC test system as claimed in claim 21, wherein each of said pin electronics units includes a first switch having one terminal connected to said distributing means, a second switch having one terminal connected to said test result judging means, a third switch having one terminal connected to each of said input/output pins and the other terminals of said first, second and third switches are connected in common.

26. An IC test system as claimed in claim 21, wherein said pattern generating means includes a driver circuit for supplying said test signal pattern to said test result judging means.