Device for computing a sliding and nonrecursive discrete Fourier transform and its application to a radar system

• US 4,929,954 A
• Filed: 09/23/1986
• Issued: 05/29/1990
• Est. Priority Date: 09/24/1985
• Status: Expired due to Fees

• Current Assignee: Thomson-CSF
• Original Assignee: Thomson-CSF
• Inventors: Elleaume, Philippe
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): SWANN, TOD R
• Application Number:
  US06/910,578
• Time in Patent Office: 1,344 Days
• Field of Search: 342/196, 342/194, 364/726, 364/827
• US Class Current: 342/194
• CPC Class Codes: G01S 13/284 using coded pulses
• CPC Class Codes: G06F 17/141 Discrete Fourier transforms
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform

Abstract

A device for computing a nonrecursive and sliding discrete Fourier transform as applicable in particular to processing of a pulse compression radar signal has N identical and parallel stages (E_k) for receiving in each case samples of the input signal (e_m+N). Each stage comprises two complex rotation operators, two adder-subtracters and two delay circuits and delivers a signal X_k^m+1 obtained from the following equations: ##EQU1##

Claims

1. A device for computing a sliding discrete Fourier transform in a time window of duration T for producing an output representing at least one component (X_k^m+1) of said transform from N samples (x_m+N) of an input signal whose transform is to be computed, wherein said computing device has at least one stage (E_k) for receiving samples and comprising complex rotation operator means as well as adding and/or subtracting means and delay circuits for delivering said component (X_k^m+1) defined by

View Dependent Claims (2, 3, 4, 5, 6, 7)

2. A device according to claim 1, wherein said device comprises N identical stages mounted in parallel.

3. A device as recited in claim 2, and further including summing means for summing outputs of at least two of said stages, delay means for delaying an output of at least one said stage, said summing means having an input coupled to an output of one stage and an output of said delay means.

4. A device according to claim 1, wherein each stage (E_k) comprises:

first complex rotation operator means for receiving said samples (x_m+N) successively and subjecting them to a complex rotation operation in order to obtain the quantity (x'"'"'_m+N) defined by equation (3);

a first delay circuit for receiving a quantity (x'"'"'_m+N) derived from the first complex rotation operator means to delay said quantity by N sampling periods to output said delayed quantity;

means for subtracting a quantity derived from the first delay circuit from the quantity derived from the first complex rotation operator means to output a corresponding result;

means for adding the result output from the subtracting means to a quantity previously computed by said adding means to output a sum;

a second delay circuit for receiving the sum (X'"'"'_k^m+1) derived from the adding means to delay said sum by one sampling period and then to deliver said delayed sum to said adding means as the previously computed quantity;

second complex rotation operator means for receiving the sum (X'"'"'_k^m+1) derived from the adding means and subjecting said sum to a complex rotation in order to obtain said component (X_k^m+1) defined by equation (1).

5. A device according to claim 4, wherein at least one of said first and second complex rotation operator means comprises four memories, each of said memories receiving a real or imaginary part of the sample subjected to a complex rotation exp. {j·

2π

·

(k/N)·

m} and index m, each of said memories delivering a product of said part of the sample and a real or imaginary part of the above exponential, sum means responsive to the products delivered by said memories for summing to form an output of said complex rotation operator means.

6. A device as recited in claim 5, and further including amplitude-weighting means coupled to outputs of said stages.

7. A radar system equipped with a radar signal receiving chain and a means for performing matched filtering and pulse compression, wherein said means for performing matched filtering and pulse compression include a device as recited in claim 1.