Non-volatile semiconductor memory device and method of the manufacture thereof

• US 4,929,988 A
• Filed: 08/23/1988
• Issued: 05/29/1990
• Est. Priority Date: 08/25/1987
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshikawa, Kuniyoshi
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/235,121
• Time in Patent Office: 644 Days
• Field of Search: 357/23.5, 357/49, 357/54, 357/55, 357/59, 357/71, 357/67, 365/185
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A groove is formed in a P well region to extend in a predetermined direction, and the groove is selectively filled with silicon dioxide layers so that the groove is separated into a plurality of groove portions. On each of opposed side walls of the groove portion along the direction of extension of the groove sequentially formed are a first gate insulating layer and a polysilicon layer serving as a floating gate electrode. Further, a second gate insulating layer and a polysilicon layer serving as a control gate electrode are sequentially formed on the polysilicon layer. N-type diffusion regions serving as source regions of MOS transistors are formed in the surface of the P well region, and further an N-type diffusion region serving as drain regions of the MOS transistors is formed in a surface region of the P well region that is located at the bottom of the groove portion.

Claims

1. A non-volatile memory device comprising:

first semiconductor region of a first conductivity type;

a groove formed in said first semiconductor region to extend in a predetermined direction;

insulating separation regions formed to selectively fill the inside of said groove so that said groove is divided into a plurality of groove portions;

a second semiconductor region of a second conductivity type formed in a surface of said first semiconductor region and serving as a source region;

a pair of first gate insulating layers formed on opposed side walls of a groove portion of said plurality of groove portions defined by said insulating separation regions and said first semiconductor region, said side walls extending along the direction of extension of said groove;

a pair of floating gate electrodes formed on surfaces of said first gate insulating layers opposite to surfaces of said first gate insulating layers contacting said side walls of said groove portion, with said floating gate electrodes having tops on a plane different from a plane of a top of said second semiconductor region;

a pair of second gate insulating layers formed on surfaces of said floating gate electrodes opposite to surfaces thereof contacting said first gate insulating layers;

a pair of control gate electrodes formed on surfaces of said second gate insulating layers opposite to surfaces thereof contacting said floating gate electrodes;

a third semiconductor region of said second conductivity type formed in a surface region of said first semiconductor region and located at a bottom of said groove portion, said third semiconductor region serving as a drain region; and

a fourth semiconductor region formed within said groove portion and contacting said third semiconductor region, said fourth semiconductor region being doped with impurities of said second conductivity type.

2. A non-volatile semiconductor memory device according to claim 1, wherein said floating gate electrodes are each formed of a polysilicon layer doped with N-type or P-type impurities, and said control gate electrodes are each formed of a polysilicon layer doped with N-type and P-type impurities.

3. A non-volatile semiconductor memory device according to claim 2, wherein said floating gate electrodes are each formed of a polysilicon layer doped with N-type or P-type impurities, and said central gate electrodes are each formed of a polysilicon layer and a refractory metal silicide layer.

4. A non-volatile semiconductor memory device according to claim 1, wherein said insulating separation regions formed within said groove portion are provided with a predetermined angle of slant along the direction of extension of said groove.

5. A non-volatile semiconductor memory device according to claim 4, wherein said angle of slant is less than 45 degrees.

6. A non-volatile semiconductor memory device according to claim 1, wherein said insulating separation regions are each formed of a silicon dioxide layer.

7. A non-volatile semiconductor memory device according to claim 1, wherein said side walls of said groove portion are formed vertically with respect to the surface of said first semiconductor region.