Architecture for an improved performance of a programmable logic device

• US 4,930,097 A
• Filed: 12/30/1988
• Issued: 05/29/1990
• Est. Priority Date: 12/30/1988
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ledenbach, Gregory W., Allen, Michael J.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/292,464
• Time in Patent Office: 515 Days
• Field of Search: 364/716, 307/465
• US Class Current: 708/230
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable

Abstract

A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and non-inverting buffer, wherein the memory cells are coupled to enable the buffers. The stored state of each of the memory cells determines if a corresponding buffer is to be activated. In one embodiment, a memory cell is provided for each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the outputs of each pair of complementary buffers are inputted to a multiplexer, wherein a corresponding memory cell coupled to its multiplexer controls the selection of the signal or its complement to be outputted.

Claims

1. In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, an apparatus for operating on said inputs according to a stored program, comprising:

a plurality of memory cells for storing said program;

a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output;

for each said buffer, a corresponding one of said memory cells is coupled to enable said buffer for passing said input signal as said corresponding output, wherein enablement of each said buffer is determined by a stored state of its corresponding memory cell and wherein said corresponding output from each said buffer provides for said plurality of outputs from said PLD.

2. The apparatus of claim 1 wherein each said buffer is comprised of an inverter and a non-inverter such that one of said inverter and non-inverter is enabled by its buffer'"'"'s corresponding memory cell.

3. The apparatus of claim 2 wherein outputs from each pair of said inverter and non-inverter are coupled together as inputs to an AND gate.

4. The apparatus of claim 3 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).

5. The apparatus of claim 4 wherein said memory cells are arranged in an array and selective pairs of inverter and non-inverter outputs are coupled to one of a plurality of AND gates and an output from each AND gate provides for a product term for said PLD.

6. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, wherein said outputs are determined by a stored program operating on said inputs, comprising:

a plurality of memory cells arranged in an array for storing said program;

a plurality of buffers for buffering said inputs if enabled, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter;

for each said buffer, a corresponding one of said memory cells is coupled to enable its buffer for passing said input signal or its complement, wherein enablement of each said buffer is determined by a stored state of said corresponding memory cell.

7. The PLD of claim 6 wherein each said buffer also provides level translation of said input.

8. The PLD of claim 7 wherein outputs from each pair of said inverter and non-inverter are coupled together to provide an input to an AND logic means to determine a product term from said array.

9. The PLD of claim 8 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).

10. The PLD of claim 9 wherein said buffers are distributed within said array and disposed proximate to said corresponding memory cell.

11. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising:

a plurality of memory cells for storing said program;

a plurality of buffers wherein each of said inputs is coupled to at least one of said buffers;

a plurality of multiplexers (MUXs) each coupled to a corresponding buffer for receiving an output from its corresponding buffer as its input;

for each said MUX, a corresponding one of said memory cells is coupled to enable said MUX for passing its input signal as an output from said MUX, wherein enablement of said MUX is determined by a stored state of said corresponding memory cell.

12. The PLD of claim 11 wherein said buffer for each said input is comprised of an inverter and a non-inverter and outputs of said inverter and non-inverter are coupled as a complement pair of inputs to its MUX and said corresponding memory cell for its MUX selects between said complement pair of inputs.

13. The PLD of claim 12 wherein outputs from said MUXs are coupled together to provide an input to an AND logic means to determine a product term from said PLD.

14. The PLD of claim 13 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).

15. A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising:

a plurality of memory cells arranged in an array for storing said program;

a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter;

a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive its input and its complement;

for each said MUX, a corresponding one of said memory cells is coupled to select between its corresponding input or its complement, wherein selection of said MUX is determined by a stored state of said corresponding memory cell.

16. The PLD of claim 15 wherein each said buffer also provides level translation of said input.

17. The PLD of claim 16 wherein outputs from said MUS are coupled together to provide an input to an AND logic means to determine a product term from said PLD.

18. The PLD of claim 16 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).