Method and device for transmitting a digital engineering service channel by means of the parity channel of a digital bit stream transmitted in a code with parity checking

• US 4,930,127 A
• Filed: 12/15/1988
• Issued: 05/29/1990
• Est. Priority Date: 12/17/1987
• Status: Expired due to Fees

• Current Assignee: Societe Anonyme DBA
• Original Assignee: Societe Anonyme DBA
• Inventors: Abaziou, Jean-Luc, Billy, Jean-Claude, Le Mouel, Bernard
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/284,579
• Time in Patent Office: 530 Days
• Field of Search: 370/110.1, 370/110.4, 370/111, 370/11, 371/49, 371/55, 371/49.1
• US Class Current: 370/529
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0063 Single parity check
• CPC Class Codes: H04L 25/4906 using binary codes

Abstract

The method enables transmission of a digital service channel by means of the parity channel of a digital bit stream transmitted in a parity checking code with parity words inserted at specific times by modifying certain parity words violating the parity checking code parity law. It consists in modifying spaced groups of even number of consecutive parity words so as not to disrupt analog detection of line errors. A digital service channel insertion circuit is included among the component parts of an MBIPIC type encoder whereby the data of a digital bit stream is transmitted by consecutive code words each formed of a block of data bits completed by a parity bit and an inversion bit. The digital service channel insertion circuit includes a modulator operative in a first computation logic circuit delivering the real value of the parity bit and a shaper circuit which strobes the digital service channel data at a timing rate that is low compared with that of the code words and selectively applies to the modulator according to the result of said strobing a pulse having the width of two code words.

Claims

1. Method of transmitting a digital service channel by means of the parity channel of a digital bit stream transmitted in a code with parity checking with parity words inserted at specific times by modifying spaced groups of even numbers of consecutive parity words to violate the parity law of the parity checking code.

2. Method according to claim 1 wherein the data of the service channel bit stream is transmitted in the parity channel of the parity checking digital code bit stream by modifying groups of two consecutive parity words causing in each group two consecutive violations of the parity checking code parity law.

3. Method according to claim 1 applied to a digital bit stream transmitted in MB1C1P type parity checking code in which the data is transmitted by consecutive code words each formed of a block of data bits completed by a parity bit and by an inversion bit indicating whether said block and its parity bit have been inverted to keep the running digital sum within limits wherein the service channel digital bit stream data is transmitted by complementing spaced groups of two parity bits belonging to two consecutive code words before selective inversion of the code words concerned.

4. Device for implementing a method of transmitting a digital service channel by means of the parity channel of a digital bit stream transmitted in a code with parity checking with parity words inserted at specific times by modifying spaced groups of even numbers of consecutive parity words to violate the parity law of the parity checking code in a parity checking code encoder and decoder, said encoder comprising a computation logic circuit adapted to determine the values of the parity words and a multiplexer adapted to define in the encoded bit stream temporal windows for insertion of parity words and said decoder comprising a parity checking code parity law violation detector circuit, which device comprises:

means for inserting digital service channel data into the parity channel which operate in said encoder and comprise a shaper circuit adapted to strobe the digital service channel data at the timing rate of spaced groups of parity words and to deliver samples occupying the duration of a group, a computation logic circuit in said encoder adapted to determine the values of the parity words and a modulator circuit which is commanded by said shaper circuit at the output of said computation logic circuit, and

digital service channel extraction means which are operative in said decoder on the signal from said parity law violation detector circuit and adapted to deduce the digital service channel data values from parity law violations detected on an even number of consecutive parity words.

6. Device according to claim 4 wherein said service channel extraction means include a discriminator adapted to recognize detection of parity law violations on two consecutive parity words and which comprises a modulo 2 counter associated with a count window limiter circuit both operating on the signal delivered by said parity law violation detector circuit forming part of said decoder, said count window limiter circuit being adapted to maintain outside its triggering period said modulo 2 counter in a first state and to release said modulo 2 counter over a duration equal to that between two consecutive parity words when it is triggered by the detection of a parity violation, said modulo 2 counter being adapted to indicate parity law violations on two consecutive parity words by a premature return to its first state during triggering of said count window limiter circuit.

5. Device for implementing a method of transmitting a digital service channel by means of the parity channel of a digital bit stream transmitted in a code with parity checking with parity words inserted at specific times by modifying spaced groups of even numbers of consecutive parity words to violate the parity law of the parity checking code applied to a digital bit stream transmitted in MB1C1P type parity checking code in which the data is transmitted by consecutive code words each formed of a block of data bits completed by a parity bit and by an inversion bit indicating whether said block and its parity bit have been inverted to keep the running digital sum within limits wherein the service channel digital bit stream data is transmitted by complementing spaced groups of two parity bits belonging to two consecutive code words before selective inversion of the code words concerned, which device is implemented in an encoder and decoder of the MB1C1P type, said encoder comprising a computation logic circuit adapted to deliver the normal value of the parity bit, an inverter circuit adapted to receive said normal value, an inversion control circuit adapted to control said inverter circuit and a multiplexer adapted to define in the encoded bit stream windows for inserting inversion bits and parity bits, and said decoder comprising a word timing recovery circuit provided with a parity law violation detector circuit, which device comprises:

means for inserting digital service channel binary data into the parity channel which are operative in said encoder and include a shaper circuit adapted to strobe the digital service channel binary data at the timing rate of spaced groups of two parity bits belonging to two consecutive code words and to deliver samples occupying the duration of a group (that is to say, two code words), said computation logic circuit adapted to deliver the normal value of the parity bit and a modulator circuit controlled by said shaper circuit at the output of said computation logic circuit adapted to substitute for said normal value of the parity bit a modified value, and

digital service channel extraction means which are operative in said decoder on the signal from said parity law violation detector circuit and are adapted to deduce the digital service channel data values from parity law violations detected on two consecutive parity bits.