Spread spectrum communication system

• US 4,930,139 A
• Filed: 05/31/1989
• Issued: 05/29/1990
• Est. Priority Date: 05/31/1989
• Status: Expired due to Fees

• Current Assignee: O'Neill Communications Incorporated
• Original Assignee: O'Neill Communications Incorporated
• Inventors: Nossen, Steve J., Simpson, Raymond W., Chandler, Donald G.
• Primary Examiner(s): Cangialosi, Salvatore
• Application Number:
  US07/359,206
• Time in Patent Office: 363 Days
• Field of Search: 375/1, 380/9, 380/49, 380/50, 380/34
• US Class Current: 375/130
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713

Abstract

The spread spectrum digital communication system includes data input devices for generating digital information signals to be transmitted using radio signals. A chip stream generator converts the data bits into chip streams that are either complemented or not complemented via an exclusive-OR gate, depending on the data bits. A scrambler further randomizes the chip stream for transmission. The receiver includes a descrambler and a correlator or digital matched filter for detecting the data signal. A modified receiver includes a sampler for sampling the scrambled signal at a rate which is the multiple of the chip rate thereby eliminating any need for recovering the chip clock. Another modified version includes a receiver having means for generating multi-level signals indicating the quality of the probable detection.

Claims

1. A digital communication system comprising:

input means for inputting a digital information signal, at a data rate, to be transmitted;

a chip stream generator means connected to said input means for converting said information signal into a chip stream having a chip rate greater than said data rate;

scrambler means for scrambling said chip stream to produce a scrambled chip stream signal; and

output means connected to said scrambler means for transmitting said scrambled chip stream signal as a radio signal.

2. The system of claim 1 wherein said chip stream generator means includes a chip code generator means for generating an n-bit chip code for each data bit, and gate means for outputting the n-bit chip code or the complement of the n-bit chip code for different values of said data bit.

3. The system of claim 2 wherein said scrambler means includes means for scrambling said chip stream using a period of more than n chips.

4. The system of claim 1 further comprising:

a descrambler means connected to said scrambled chip stream;

a receiver means for receiving and detecting said receiver means for converting the detected scrambled chip stream into an unscrambled chip stream; and

a data detector means connected to said descrambler means for detecting said data signal.

5. The system of claim 4 wherein said detector means is a correlator.

6. The system of claim 5 wherein said correlator is a digital matched filter.

7. The system of claim 6 wherein said chip stream generator means includes a chip code generator means for generating an n-bit chip code for each data bit, and gate means for outputting the n-bit chip code or the complement of the n-bit chip code for different values of said data bit.

8. The system of claim 7 wherein said scrambler means includes means for scrambling said chip stream using a period of more than n chips.

9. The system of claim 1 further comprising:

a receiver means for receiving and detecting said transmitted scrambled chip stream;

a sampler means connected to said receiver means for sampling said detected scrambled chip stream at a sampling rate which is a multiple of the rate of said chip stream;

descrambler means connected to said sampler means for converting the output thereof into an unscrambled chip stream having a rate equal to said sampling rate; and

data detector means connected to said descrambler means for detecting said data signal.

10. The system of claim 9 wherein said detector means is a correlator.

11. The system of claim 10 wherein said correlator is a digital matched filter.

12. The system of claim 11 wherein said chip stream generator means includes a chip code generator means for generating an n-bit chip code for each data bit, and gate means for outputting the n-bit chip code or the complement of the n-bit chip code for different values of said data bit.

13. The system of claim 12 wherein said scrambler means includes means for scrambling said chip stream using a period of more than n chips.

14. The system of claim 1 further comprising:

a receiver means for receiving and detecting said transmitted scrambled chip stream;

a sampler means connected to said receiver means for sampling the detected chip stream and encoding the samples into a series of first multi-level signals as a function of the level of said sample;

descrambler means connected to said sampler means for descrambling said chip stream including converting the output thereof into a second multi-level signal; and

data detector means connected to said descrambler means for detecting said data signal.

15. The system of claim 14 wherein said descrambler means includes a multiplier means for multiplying at least two spaced values of said first multi-level signal to produce said second multi-level signal.

16. The system of claim 15 wherein said spaced values are spaced a distance greater than the length of one chip stream.

17. The system of claim 14 wherein said data detector means is a correlator.

18. The system of claim 17 wherein said correlator is a digital matched filter.

19. The system of claim 17 wherein said correlator includes a multi-level digital matched filter including means for digitally encoding said second multi-level signal.