Digital to analog signal converter

• US 4,931,795 A
• Filed: 08/09/1989
• Issued: 06/05/1990
• Est. Priority Date: 08/09/1989
• Status: Expired due to Term

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Gord, John C.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Logan, Sharon D.
• Application Number:
  US07/391,437
• Time in Patent Office: 300 Days
• Field of Search: 341/135, 341/144
• US Class Current: 341/135
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H04R 25/606 acting directly on the eardrum, the ossicles or the skull, e.g. mastoid, tooth, maxillary or mandibular bone, or mechanically stimulating the cochlea, e.g. at the oval window

Abstract

A D to A converter comprising a series of stages each including a current mirror having an input and an output transistor (Q1 and Q3) and a current adjusting transistor (Q2, Q4) connected in parallel with each input and output transistor for adjusting the output current from the current mirror as a function of the operating states of the current adjusting transistors. The operating state of each current adjusting transistor is controlled by a digital signal applied to a switch (Q2S, Q2S'"'"') connected to the gate of each current adjusting transistor. Each stage also includes a control circuit (Q1C, Q3C) for maintaining equal the drain voltages of its input and output transistors whereby the current changes introduced in the output current of the converter stage are functions of the relative geometric sizes of the input, output and current adjusting transistors comprising the converter stage.

Claims

1. A D to A converter stage comprising:

a current mirror including an input transistor and an output transistor connected to a supply voltage, the input transistor also being connected to a reference current source and the output transistor being connected to an output for the current mirror;

a current adjusting transistor in parallel with each of the input and output transistors for adjusting the output current of the current mirror as a function of the operating states of the current adjusting transistors;

digital signal activated switch means for selectively controlling operation of each current adjusting transistor; and

circuit means for regulating drain voltages on the input and output transistors whereby the values of currents flowing in the input and output transistors and hence the value of the output current is a direct function of the relative geometric sizes of the input, output and current adjusting transistors.

2. The converter stage of claim 1 wherein the switch means comprises a switch connected to a gate of each current adjusting transistor.

3. The converter stage of claim 1 wherein the input transistor includes a drain and a gate connected to a gate of the output transistor and a source connected to a source of the output transistor and to the supply voltage.

4. The converter stage of claim 3 wherein each current adjusting transistor has a source connected to the supply voltage and a drain connected to a drain of the input or output transistor to which it is connected in parallel and wherein the switching means for each current adjusting transistor comprises a series circuit including a first switching transistor connected between the gate and source of the current adjusting transistor and a second switching transistor connected between the gate and drain of the current regulating transistor, each switching transistor being selectively controlled by a digital signal applied thereto.

5. The converter stage of claim 1 wherein the circuit means for regulating the drain voltages in the input and output transistors comprises a first control transistor having a source connected to a drain of the input transistor and a gate and drain connected together and to the reference current source and a second control transistor having a source connected to a drain of the output transistor and a gate connected to the drain of the first control transistor whereby substantially the same gate to source voltages are applied to the first and second control transistors and the input and output transistors see substantially the same drain voltage.

6. A D to A converter comprising:

a series of current mirrors each including an input and an output transistor connected to a supply voltage, a first one of the input transistors being connected to a reference current source, each output transistor being connected to a output for the current mirror in which it is included;

a current adjusting transistor in parallel with each input and output transistor for adjusting the output current of the current mirror in which it is included as a function of its operating state;

digital signal activated switch means for selectively controlling operation of each current adjusting transistor; and

circuit means for regulating drain voltages on each input and output transistor whereby the values of currents flowing in the input and output transistors and hence the value of each current mirror output current is a direct function of the relative sizes of the input, output and current adjusting transistors comprising the current mirror.

7. The converter of claim 6 wherein each input transistor includes a drain and gate connected to a gate of an associated output transistor included in the current mirror including the input transistor and a source connected to a source of the associated output transistor and to the supply voltage.

8. The converter of claim 7 wherein each current adjusting transistor has a source connected to a supply voltage and a drain connected to a drain of the input o output transistor to which it is connected in parallel and wherein the switch means for each current adjusting transistor comprises a series circuit including a first switching transistor connected between the gate and source of the current adjusting transistor and a second switching transistor connected between the gate and drain of the current adjusting transistor, each switching transistor being selectively controlled by a digital signal applied thereto.

9. The converter of claim 8 wherein the circuit means for regulating the drain voltages in the input and output transistors comprises for each current mirror:

a first control transistor having a source connected to a drain of the input transistor included in the current mirror and a gate and drain connected together at a junction, the gate and drain junction for the first control transistor connected to the first one of the input transistors being connected to the reference current source and the gate and drain junctions for all other first control transistors being connected to an output terminal for the immediately prior current mirror to receive the output current thereof, and

a second control transistor having a source connected to the drain of the output transistor included in the current mirror and a gate connected to the drain of the first control transistor for the current mirror whereby substantially the same gate to source voltages are applied to the first and second control transistors and the input and output transistors of each current mirror will see substantially the same drain voltage.

10. A D to A converter stage comprising:

a current mirror including an input transistor and an output transistor connected to a supply voltage, the input transistor also being connected to a reference current source and the output transistor being connected to an output for the current mirror;

a current adjusting transistor in parallel with each of the input and output transistors for adjusting the output current of the current mirror as a function of the operating states of the current adjusting transistors; and

digital signal activated switch means connected to a gate of each current adjusting transistor for selectively controlling operation of each current adjusting transistor.

11. The converter stage of claim 10 wherein each current adjusting transistor has a source connected to the supply voltage and a drain connected to a drain of the input or output transistor to which it is connected in parallel and wherein the switching means for each current adjusting transistor comprises a series circuit including a first switching transistor connected between the gate and source of the current adjusting transistor and a second switching transistor connected between the gate and drain of the current adjusting transistor, each switching transistor being selectively controlled by a digital signal applied thereto.